Fraunhofer-Institut für Zuverlässigkeit und Mikrointegration IZM

Filters

Reset filters

Settings
Now showing 1 - 10 of 115
  • Publication
    Smart sensor systems for extremely harsh environments
    ( 2021)
    Kappert, Holger
    ;
    Schopferer, Sebastian
    ;
    Döring, Ralf
    ;
    Ziesche, Steffen
    ;
    Olowinsky, Alexander
    ;
    Naumann, Falk
    ;
    Jägle, M.
    ;
    Ostmann, Andreas
    Sensors systems are key elements for capturing environmental properties and are increasingly important in industry 4.0 for the intelligent control of processes. However, under harsh operating conditions like high temperatures, high mechanic load or aggressive environments, standard electronics cannot be used. Eight Fraunhofer institutes have therefore bundled their competencies in sensors, microelectronics, assembly, board design, laser applications and reliability analysis to establish a technology platform for sensor systems working under extreme conditions.
  • Publication
    On the feasibility of fan-out wafer-level packaging of capacitive micromachined ultrasound transducers (CMUT) by using inkjet-printed redistribution layers
    ( 2020)
    Roshanghias, A.
    ;
    Dreissigacker, M.
    ;
    Scherf, C.
    ;
    Bretthauer, C.
    ;
    Rauter, L.
    ;
    Zikulnig, J.
    ;
    Braun, T.
    ;
    Becker, K.-F.
    ;
    Rzepka, S.
    ;
    Schneider-Ramelow, M.
    Fan-out wafer-level packaging (FOWLP) is an interesting platform for Microelectromechanical systems (MEMS) sensor packaging. Employing FOWLP for MEMS sensor packaging has some unique challenges, while some originate merely from the fabrication of redistribution layers (RDL). For instance, it is crucial to protect the delicate structures and fragile membranes during RDL formation. Thus, additive manufacturing (AM) for RDL formation seems to be an auspicious approach, as those challenges are conquered by principle. In this study, by exploiting the benefits of AM, RDLs for fan-out packaging of capacitive micromachined ultrasound transducers (CMUT) were realized via drop-on-demand inkjet printing technology. The long-term reliability of the printed tracks was assessed via temperature cycling tests. The effects of multilayering and implementation of an insulating ramp on the reliability of the conductive tracks were identified. Packaging-induced stresses on CMUT dies were further investigated via laser-Doppler vibrometry (LDV) measurements and the corresponding resonance frequency shift. Conclusively, the bottlenecks of the inkjet-printed RDLs for FOWLP were discussed in detail.
  • Publication
    Plattformkonzept zum Aufbau von hochintegrierten Multisensorknoten
    ( 2019)
    Becker, Karl-Friedrich
    ;
    Böttcher, Mathias
    ;
    Schiffer, Michael
    ;
    Pötter, Harald
    ;
    Brockmann, Carsten
    ;
    Freimund, Damian
    ;
    Tschoban, Christian
    ;
    Windrich, Frank
    ;
    Braun, Tanja
    ;
    Hopsch, Fabian
    ;
    Heinig, Andy
    ;
    Voigt, Sven
    ;
    Baum, Mario
    ;
    Hofmann, Lutz
    ;
    Lang, Klaus-Dieter
    Diese Veröffentlichung stellt das Konzept und die dazugehörige Packaginglösung einer universellen IoT Sensorplattformmit einer System-on-Chip (SoC) Familie als zentrale Steuer- und Recheneinheit vor. Die Plattform besteht aus 4 Ebenen, die angefangen vom hochintegrierten SoC, über die Montagemöglichkeit von gehäusten wie auch ungehäusten Sensoren bis hin zum System Board, was die üblichsten drahtgebundenen und drahtlosen Schnittstellen zur Verfügung stellt. Das Layout zur Sensormontage kann auf individuelle Kundenwünsche angepasst werden, um so spezielle Anforderungen an die Messaufgabe zu ermöglichen. Die Kerntechnologie des Packages besteht aus einem Moldpackage in Fan-Out Technologiemit unterseitiger Umverdrahtung des SoC zu den Balling Pads und Durchführungen zur oberseitigen Umverdrahtungfür die Montage der Sensoren.
  • Publication
    Functional integration - structure-integrated wireless sensor technology targeting smart mechanical engineering applications
    ( 2018)
    Rülke, Steffen
    ;
    Beyer, Volkhard
    ;
    Zorn, Wolfgang
    ;
    Meinig, Marco
    ;
    Wecker, Julia
    ;
    Reuter, Danny
    ;
    Deicke, Frank
    ;
    Clausner, André
    ;
    Werner, Thomas
    Functional integration on the micro/nano scales enables smart functionalities in mechanical engineering systems. Here, exemplarily shown for a ball screw drive, a structure-integrated wireless sensor technology is implemented into a manufacturing system for advanced process control and status monitoring - even at machine components being not yet accessible or difficult to access. This includes also a miniaturized, networked and energy-efficient information and communication technology (ICT) integrated into the machine.
  • Publication
    A Novel Concept for Accelerated Stress Testing of Thermal Greases and In-situ Observation of Thermal Contact Degradation
    ( 2018)
    Wunderle, B.
    ;
    May, D.
    ;
    Heilmann, J.
    ;
    Arnold, J.
    ;
    Hirscheider, J.
    ;
    Li, Y.
    ;
    Bauer, J.
    ;
    Ras, M.A.
    Thermal greases allow a low stress bond at low bond line thicknesses (BLT) at medium thermal conductivities and simple application, all of which make it an alternative to solders, thermal adhesives or pads. It is widely used in power and microprocessor applications, most of which involve large areas to be used for heat transfer. However, for years thermal overload failure of power modules and chips has been a pressing problem due to pump-out of thermal grease as die or module thermal interface material (TIM): Most thermal greases are Bingham fluids and thus not solids, so they can be squeezed out from in between the gap, driven by thermo-mechanical action of the adjacent layers as e.g. DCB substrate or silicon chip with the heat sink. Today, thermal greases have to be qualified in lengthy stress tests in a product relevant environment which consumes substantial resources as often a system test is required. Therefore, a fast test is necessary which accelerates testing and thus allows a fast screening of commercial greases on one hand, and guidelines for material development on the other. For that purpose this paper addresses this topic in a combined simulative and experimental way, where at the same time a novel test procedure is proposed for accelerated grease pump-out testing (GPOT) in the framework of a completely new approach, combining loading with in-situ failure analytical techniques and decoupling thermal from mechanical loading. This allows for the first time a realistic loading of greases during accelerated testing. The method is demonstrated on various commercial and custom greases, varying their composition and structure, and benchmarked against industry standard thermal cycling tests.
  • Publication
    Transient thermal storage of excess heat using eutectic BiSn as phase change material for the thermal management of an electronic power module
    ( 2018)
    Wunderle, B.
    ;
    Springborn, M.
    ;
    May, D.
    ;
    Heilmann, J.
    ;
    Manier, C.-A.
    ;
    Abo Ras, M.
    ;
    Oppermann, H.
    ;
    Sarkany, Z.
    ;
    Mitova, R.
    Novel concepts in power electronics rely heavily on the availability and processability of new materials and packaging technologies to meet the requirements of increasing performance and reliability at lower form factor, weight and cost. Today's main technological route for converter modules is still the power die soldered and wire-bonded to a DCB substrate. New applications or semiconductor technologies like e.g. SiC, however, require enhanced thermal management using standard commercial casings within the same, usually very limited thermal budget. This paper is the final of a series of publications dealing with a novel thermal management concept for power electronics enabled by the use of advanced packaging technologies as well as smart handling of power transients, making use of a TEC and a thermal buffer using a low melting BiSn eutectic as phase change material to store excess heat temporarily exploiting the PCM's enthalpy of fusion. This concept is exemplified on a typical six-pack converter module for industrial applications (4 kW, 1200 Volts) to be integrated into a standard easyPIM casing while being able to cope with overload power pulses. This paper summarises the whole system approach, references back to literature for details finishes the series of papers with the reliability analysis of the buffer technology. Thus, all stages of product development covering design, technology and performance are finally highlighted.
  • Publication
    Thermo-mechanical characterisation of thin sputtered copper films on silicon: Towards elasto-plastic, fatigue and subcritical fracture-mechanical data
    ( 2018)
    Wunderle, B.
    ;
    May, D.
    ;
    Zschenderlein, U.
    ;
    Ecke, R.
    ;
    Springborn, M.
    ;
    Jöhrmann, N.
    ;
    Pareek, K.A.
    ;
    Heilmann, J.
    ;
    Stiebing, M.
    ;
    Arnold, J.
    ;
    Dudek, R.
    ;
    Schulz, S.
    ;
    Wolf, M.J.
    ;
    Rzepka, S.
    Thin metal layers, especially those made of copper, are omnipresent in today's packaging applications as e.g. RDL structures, conductor traces on flexible and stretchable substrates, chip finishes or terminal metallisation, serving electrical, thermal or mechanical purposes. During operation, thermo-mechanical stress will cause failures in the Cu layers and interfaces over time. As Cu is very process and size dependent, its resistance to fatigue failure needs to be characterised with samples which have undergone identical processing steps as those in the real application. For that purpose, simple specimens and fast testing routines are necessary, some of which may need special loading stages for varying the load variables of interest such as stress amplitude and temperature. This paper addresses fatigue characterisation of thin Cu films on silicon under typical processing conditions on simple and inexpensive but industry-grade samples. Along with them, custom built test stands have been used to handle those specimens appropriately within a specimen-centred approach.
  • Publication
    Modelling and characterisation of a grease pump-out test stand and its use for accelerated stress testing of thermal greases
    ( 2017)
    Wunderle, B.
    ;
    Heilmann, J.
    ;
    May, D.
    ;
    Arnold, J.
    ;
    Hirscheider, J.
    ;
    Bauer, J.
    ;
    Schacht, R.
    ;
    Vogel, J.
    ;
    Ras, M.A.
    Thermal greases allow a low stress bond at low bond line thicknesses (BLT) at medium thermal conductivities and simple application, all of which make it an alternative to solders, thermal adhesives or pads. It is widely used in power and microprocessor applications, most of which involve large areas to be used for heat transfer. However, for years thermal overload failure of power modules and chips has been a pressing problem due to pump-out of thermal grease as die or module thermal interface material (TIM): Most thermal greases are Bingham fluids and thus no solids, so they can be squeezed out from in between the gap, driven by thermo-mechanical action of the adjacent layers as e.g. DCB substrate or silicon chip with the heat sink. Today, thermal greases have to be qualified in lengthy stress tests in a product relevant environment which consumes substantial resources as often a system test is required. Therefore, a fast test is necessary which accelerates testing and thus allows a fast screening of market-available greases on one hand, and guidelines for material development on the other. For that purpose this paper addresses this topic in a combined simulative and experimental manner, where at the same time a novel test procedure is proposed for accelerated grease pump-out testing (GPOT) in the framework of a completely new approach, combining loading with in-situ failure analytical techniques and decoupling thermal from mechanical loading.
  • Publication
    Correlation between mechanical material properties and stress in 3D-integrated silicon microstructures
    ( 2017)
    Stiebing, M.
    ;
    Vogel, D.
    ;
    Steller, W.
    ;
    Wolf, M.J.
    ;
    Zschenderlein, U.
    ;
    Wunderle, B.
    Three-dimensional (3D) electronic systems enable higher integration densities compared to their 2D counterparts, a gain required to meet the demands of future exa-scale computing, cloud computing, big data systems, cognitive computing, mobile devices and other emerging technologies. Through-silicon vias (TSVs) open a pathway to integrate electrical connections for signaling and power delivery through the silicon (Si) carrier used in 3D-stacked microstructures. As a limitation, TSVs induce locally thermomechanical stress in the Si lattice due to a mismatch in the coefficients of thermal expansion between Si and the TSV-filling metals and therefore enforce temperature related expansion and shrinkage during the annealing cycle. This temperature-induced crowding and relaxation of the Si lattice in proximity of the TSV (called 'keep-out-zone' forbidden for active device positioning) can cause a variety of issues ranging from stress-induced device performance degradation, interfacial delamination or interconnect failures due to cracking of the bond or even of the entire Si microstructures at stress hotspots upon assembly or operation. Additionally also the interconnect structures induce stress that will overlap with the TSV induced stress.
  • Publication
    Stress investigations in 3D-integrated silicon microstructures
    ( 2016)
    Stiebing, M.
    ;
    Lörtscher, E.
    ;
    Steller, W.
    ;
    Vogel, D.
    ;
    Wolf, M.J.
    ;
    Brunschwiler, T.
    ;
    Wunderle, B.
    With the anticipated slow-down of Moore's Law in the near future, three-dimensional (3D) packaging of microelectronic structures would enable to further increase the integration density required to meet the forecasted demands of future exa-scale computing, cloud computing, big data systems, cognitive computing, mobile communicatoin and other emerging technologies. Through-silicon vias (TSVs) are a pathway to provide electrical connections for signaling and power-delivery through 3D-stacked silicon (Si) microstructures. TSVs and related structures such as, e.g., interconnects and redistribution lines, however, induce stress in their proximity, namely upon electrochemical deposition and subsequent annealing, the latter due to the large mismatch in the coefficient of thermal expansion between Si and the TSV-filling materials used.