Fraunhofer-Institut für Zuverlässigkeit und Mikrointegration IZM

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Experimental and simulative study of warpage behavior for fan-out wafer-level packaging

2022 , Dijk, Marius van , Huber, Saskia , Stegmaier, Andreas , Walter, Hans , Wittler, Olaf , Schneider-Ramelow, M.

Controlling warpage effects in fan-outwafer-level packaging (FO-WLP) is of key importance for realizing reliable and cost-efficient system in packages (SiPs). However, warpage effects can occur during the manufacturing process, caused by a combination of different processing temperatures, different materials, and the changing properties of the materials (e.g. polymerization and related cure shrinkage). One approach to controlling warpage could be realized by assessing a numerical simulation workflow of the FO-WLP process chain, in which the relevant material properties and geometry are used as input. Since there are many different steps included in the FO-WLP process, accompanied by complex material behavior, this workflow is not straight-forward. In the present paper, the first FO-WLP processing steps are investigated in detail by performing extensive thermo-mechanical material characterization, temperature-dependent warpage measurements, and numerical simulations. The investigation focuses on two epoxy mold compound (EMC) materials with completely different physical properties. The warpage measurements of bi-material (EMC and silicon) samples reveal an irreversible effect after passing certain processing temperatures, which are significant for final warpage at room temperature. A new approach to measuring the coefficient of thermal expansion (CTE) is discussed, using a temperature profile based on the temperature in the process, instead of the three identical temperature ramps suggested by the typical standards. This new approach makes it possible to determine possible shrinkage effects. Within the simulation model, the hysteresis effect observed in the experiment is taken into account by adding a shrinkage strain as well as changing the CTE values during the process. A very good agreement between the experiment and simulation is achieved, which is shown for several demonstrators with different epoxy mold compound materials and thicknesses.

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Panel Level Packaging - Where are the Technology Limits?

2022 , Braun, Tanja , Hölck, Ole , Obst, Mattis , Voges, Steve , Kahle, Ruben , Böttcher, Lars , Billaud, Mathilde , Stobbe, Lutz , Becker, Karl-Friedrich , Aschenbrenner, Rolf , Voitel, M. , Schein, F.-L. , Gerholt, L. , Schneider-Ramelow, M.

Fan-out Wafer and Panel Level Packaging are two of the dominating trends in microelectronics packaging. Both approaches with different flavors as RDL last face-up or face- down have reached maturity and are introduced in high volume manufacturing. For Fan-out Wafer Level Packaging (FOWLP) clear application trends and technology roadmaps do exist. These range from low density core technology for e.g. RF or PMIC (power management IC) packaging over high density application processor packaging to ultra-high-density applications for networking servers etc.. For panel level packaging it is still not fully clear if the same performance can be achieved as on wafer level as larger process / panel sizes may have higher challenges in process control, accuracy and consistency, material and equipment or handling.Main driver for moving to panel level packaging is of course lowering the packaging cost. More packages can be processed in parallel and panel formats have a much better area utilization (ratio between panel/wafer size and package size) than round wafer shapes. Also, environmentally PLP is advantageous by e.g. lower waste and smaller carbon footprint. However, for both aspects processes with sufficiently high yield are required. This is especially true for FOWLP/PLP RDL last processes as a failure in the RDL will also lead to a loss of packaged die(s).This paper describes current technology developments to access the limits of the panel level packaging technology. Warpage, die shift and fine line capabilities are the main topics here. To better understand the compression molding process as the technological basis of the reconfigured panel and its influence on warpage and die shift a dedicated sensor mold tool has been developed. By integration of temperature, pressure, dielectric and fiber Bragg grating sensors the flowing and curing behavior of epoxy molding compound can be studied in-situ. Results will support process simulations for warpage prediction and more accurate die shift compensation.For large panel processing an adaptive patterning approach might be needed anyhow to achieve a high yield. Here the combination of an intelligent assembly strategy for high speed and sufficient accuracy, capabilities to measure each die position and a maskless lithography process adapting the redistribution layer (RDL) to each die position may lead to a cost-effective high yield process.In addition, a clear trend towards finer lines and spaces as well as smaller via diameters is also demanded for large panel RDL processes. Process developments towards 2 μm lines and spaces and via shrinking on 610x457 mm2 (24'x18') panels are shown including material and process options.In summary this paper will show current PLP technology developments for future high-end applications and will cover at the same time economic and environmental aspects.

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Interconnecting embroidered hybrid conductive yarns by ultrasonic plastic welding for e-textiles

2022 , Dils, Christian , Kalas, D. , Reboun, J. , Suchy, S. , Soukup, R. , Moravcova, D. , Krshiwoblozki, Malte von , Schneider-Ramelow, M.

This article presents a novel approach for the electrical interconnection of embroidered conductive yarns with each other at defined cross-points using ultrasonic spot welding. The electrically conductive yarns are made of silver-coated copper microwires plied with polyester filament fibers into a hybrid embroidery yarn. In this study we evaluated the influence of different material properties (number of microwires of conductive yarn, fabric substrate, and adhesive film), the embroidery designs of contact pads, and the main parameters of the welding process (energy, force, amplitude, and tools) on the welded interconnection. The results were evaluated by the process yield and the contact resistance of the welded contacts. The electrical contacts were then tested for long-term reliability (elevated temperature and humidity, temperature shock change, bending, washing and drying) and analyzed. In addition, the contacts were examined with scanning electron microscopy (SEM) and micro-computed tomography and in the form of cross-sections with optical and SEM techniques to discuss interconnection and failure mechanisms. The results show that ultrasonic spot welding can enable the production of highly reliable interconnections of textile-integrated conductive yarns with contact resistances of a few milliohms that are resistant to mechanical, environmental, and washing conditions, leading to potential new manufacturing processes of e-textiles.

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Washable, Low-Temperature Cured Joints for Textile-Based Electronics

2021 , Szalapak, J. , Scenev, V. , Janczak, D. , Werft, L. , Rotzler, S. , Jakubowska, M. , Krshiwoblozki, M. von , Kallmayer, C. , Schneider-Ramelow, M.

Low-temperature die-attaching pastes for wearable electronics are the key components to realize any type of device where components are additively manufactured by pick and place techniques. In this paper, the authors describe a simple method to realize stretchable, bendable, die-attaching pastes based on silver flakes to directly mount resistors and LEDs onto textiles. This paste can be directly applied onto contact pads placed on textiles by means of screen and stencil printing and post-processed at low temperatures to achieve the desired electrical and mechanical properties below 60 °C without sintering. Low curing temperatures lead to lower power consumption, which makes this paste ecological friendly.

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A Novel Quantitative Adhesion Measurement Method for Thin Polymer and Metal Layers for Microelectronic Applications

2022 , Woehrmann, Markus , Mackowiak, Piotr , Schiffer, Michael , Lang, K.-D. , Schneider-Ramelow, M.

Advancements in packaging technologies like Fan-Out demand for a higher integration density with an increased number of RDL layers as well as novel low-k layers as interlayer dielectric. The adhesion of these layers becomes an important factor for the reliability of the packaging because an enforcement by mechanical bond is limited. This work presents a novel test method (Stripe Lift-Off Test - SLT) for the adhesion characterization of thin film layers used in RDL for Fan-In and Fan-Out. The method is based on a modified edge lift-off test (mELT) concept. A polymer layer under high tensile stress is used to force a delamination of a layer stack. A critical energy release rate (J/m2) leading to a delamination can be estimated based on the known biaxial stress in the stressing polymer. The usage of residual stress in a layer stack for driving a delamination avoids any additional clamping, gluing of additional layers or the demand of special adhesion measurement equipment. The quantified adhesion test can be integrated in any RDL production line since only coating equipment is needed as well as a dicing tool for sample generation. The sample generation complexity can be scaled regarding the purpose of the adhesion measurement - ranging from a quick, rough estimation and adhesion value evaluation in a production process to a precise prediction of the energy release rate that can be used as a basis for packaging simulation. The established mELT for the quantification of the interface's fracture toughness is limited by the fact that it is running at negative temperatures. The novelty of the SLT is a stress polymer layer with a modifiable stress state which allows the adhesion measurement at room temperature. The stress state can be tailored to investigate the delamination at a certain temperature related to the application. FE-modeling of the SLT in ANSYS is presented and these results are compared to the analytical energy release rate estimation of the SLT. These verified FEM fracture models form the basics for the integration of the SLT fracture toughness data into more complex reliability simulations of advanced packaging. Exemplary adhesion measurements are presented for polymer films as well as for sputter layers with different preconditioning.

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Finite Element Influence Analysis of Power Module Design Options

2022 , Dijk, Marius van , Wittler, Olaf , Hung, P.-C. , Lai, W.-H. , Hsieh, C.-Y. , Wang, T. , Schneider-Ramelow, M.

The electrification trend for the automotive industry (electric- and hybrid electric vehicles EV/HEV) desires the development of application specific power modules with shorter time-to-market for which the reliability is guaranteed over a large time span. Besides the electrical layout of such power modules, numerous variations of the design can be made which include material selection, the used assembly and interconnection technologies and geometrical variations like layer thicknesses and position of certain components.Due to the time efficiency, relative low costs and good possibilities for visualizing thermal and thermomechanical behavior in detail, research and development is focusing nowadays more and more on Finite Element Analysis (FEA). The possibilities of assessing finite element analysis for visualizing influences of certain design choices are discussed in this paper, where the development of a new, low-power automotive power module is used as an example. Moreover, simulation analysis focusses on the complete power module, in order to consider cross influences of design choices.First, a discussion on the static thermal behavior is presented followed by the thermomechanical behavior. As the die attach is prone to show early failure/degradation, a numerical simulation Design of Experiment (DoE) is conducted to visualize the influence of - for example - the heat sink material on die attach reliability. For this purpose, 37 simulation models are evaluated, having different configurations. Additional simulations are performed to investigate the reliability of the electrical connection (ribbon- or wire bond).Special attention is given to the reliability of sintered silver die attach technology. This trend-topic in power electronics is gaining much interest in the recent years where many authors have published results of increasing reliability when the classical soldered die attach is replaced with sintered silver. Experimental tests are performed to investigate the influence of the sintered silver Bond Line Thickness (BLT) and to verify the simulation results. The experiments indicate that even after 2500 thermal shock cycles according to the AQG324 no failure or starting degradation for all bond line thicknesses was observed.

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Influence of Ball Size and Geometry on the Reliability and RF Performance of mmWave System-in-Package: A Simulation Approach

2021 , Dilek, S. , Ndip, I. , Rossi, M. , Tschoban, C. , Kuttler, S. , Wittler, O. , Lang, K.-D. , Goetze, C. , Berger, D. , Wieland, M. , Schneider-Ramelow, M.

Solder ball reliability is a long-discussed topic in microelectronic packaging. With new package types needed for mmWave applications a trade-off between reliability and RF performance may arise, when the solder ball geometry has to be selected for specific package assemblies. In this work, the lifetime for different solder ball geometries is investigated within a numerical simulation workflow, by means of a sensitivity analysis in which the ball diameter, pad sizes and stand-off distance are varied. Next to lifetime estimations, 3D full-wave simulations have been applied to analyze the RF performance of the structures under investigation at 77-79 GHz (E-band) center frequencies relevant for automotive radar applications. Finally, the trade-off between RF performance and reliability is illustrated and quantified.

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Low-Temperature Processible Highly Conducting Pastes for Printed Electronics Applications

2022 , Scenev, V. , Szalapak, J. , Werft, Lukas , Hoelck, Ole , Jakubowska, M. , Krshiwoblozki, Malte von , Kallmayer, Christine , Schneider-Ramelow, M.

Scalable additive manufacturing of printed electronics is a growing field accompanied by increasing demands for reliable and integrable functional flexible printed electronic devices. Herein, a novel type of electrically conducting silver-based pastes for additive manufacturing is demonstrated. These pastes are designed for stencil- and screen-printing and can be post-processed at very low temperatures, at ambient. Furthermore, printed lines made with the pastes exhibit an electrical sheet resistance below 60 mΩ sq-1 even after room temperature and only 25 mΩ sq-1 after two minutes of curing at 90 °C.

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Investigation and Modeling of Etching Through Silicon Carbide Vias (TSiCV) for SiC Interposer and Deep SiC Etching for Harsh Environment MEMS by DoE

2022 , Mackowiak, Piotr , Erbacher, Kolja , Schiffer, Michael , Manier, Charles-Alix , Töpper, Michael , Ngo, H.-D. , Schneider-Ramelow, M. , Lang, K.-D.

This article presents prime results on process development and optimization of dry etching of silicon carbide (SiC) for via formation and deep etching for SiC-based microsystems. The investigations and corresponding results of the process developments enable the first realization of a full SiC-based technological demonstrator composed of a SiC-interposer with a flip chip mounted deep etched micro electromechanical system (MEMS) SiC Device. By optimizing the process, etch depth of 200 μm with an etch rate of up to 2 μm /min can be achieved for via etching. In addition, a design of experiments (DoEs) with a total of 29 experiments with seven factors was done to characterize the deep etching of large areas into the SiC. Hereby, vertical sidewalls with low micromasking, low microtrenching and an etch rate of up to 4 μm /min could be achieved. The findings and optimized processes were implemented to develop on the one hand a 200- μm -thick SiC interposer with copper metallization. On the other hand, a SiC-MEMS Device was manufactured with a deep etched cavity in SiC bulk wafer forming by the end a 50- μm thin membrane. The results demonstrate the ability of etching monocrystalline SiC with a high etch rate, enabling new fundamental topologies/structures and packaging concepts for harsh environments MEMSs and high-power electronics. The developed etching technologies demonstrate and enable various applications for 3-D Integration with wide bandgap substrates taking advantage of the superior electrical and mechanical properties of SiC.

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Fan-Out Wafer and Panel Level Packaging - A Platform for 3D Integration

2021 , Braun, T. , Becker, K.-F. , Töpper, M. , Aschenbrenner, R. , Schneider-Ramelow, M.

The constant drive to further miniaturization and heterogeneous system integration leads to a need for new packaging technologies that also allow large area processing and 3D integration with strong potential for low cost applications. Here, Fan-Out Wafer Level Packaging [FOWLP] is one of the latest packaging trends in microelectronics. The technology can be also used for multi-chip packages or System in Package (SiP). 3D integration is typically done by package on package (PoP) stacking where the electrical 3D routing is done by through mold (TMV) or through package vias (TPV) and a redistribution layer on both sides of the FOWLP. In summary the paper will give a review of the different technology approaches for through mold vias in a Fan-out Wafer or Panel Level Package.

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