Fraunhofer-Institut für Zuverlässigkeit und Mikrointegration IZM

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  • Publication
    Evaluation of thin wafer processing using a temporary wafer handling system as key technology for 3D system integration
    ( 2010)
    Zoschke, K.
    ;
    Wegner, M.
    ;
    Wilke, M.
    ;
    Jürgensen, N.
    ;
    Lopper, C.
    ;
    Kuna, I.
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    Glaw, V.
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    Röder, J.
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    Wünsch, O.
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    Wolf, M.J.
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    Ehrmann, O.
    ;
    Reichl, H.
    In this paper we describe the process integration of a temporary wafer handling system for wafer thinning and thin wafer backside processing. Thin wafer handling is a key technology and enabler for the wafer level fabrication of through silicon via (TSV) based 3D architectures. The work was done as evaluation study to prove the compatibility of a thin wafer handling system with standard processes used for thinning and backside processing of "via-first" TSV wafers as well as for thinning of bumped wafers. The used thin wafer handling system is based on perforated carrier wafers, which are bonded by an adhesive to the customer wafer and de-bonded by solvent release of the adhesive. All wafers used in this work had 200 mm format. The evaluation was run systematically in three major phases. In the first phase the main process scenarios, which require thin wafer handling, were defined. In a second phase setup trials for bonding, thinning, backside processing and debonding we re run on monitor wafers with different types of front side topography, but without TSVs. After finishing the setup trials in a third phase, the monitor wafers were replaced by wafers with copper filled TSVs, which were fabricated in "via-first" technology. Using the established thin wafer handling and processing sequence, silicon interposer wafers with 55 m thickness were manufactured. The measured via chains have via pitches of 28 m using 15 m via diameter.
  • Publication
    Heterogeneous System Integration - A Key Technology for Future Microelectronic Applications
    ( 2008)
    Reichl, H.
    ;
    Wolf, M.J.
    Heterogeneous system integration is one of the key topics for future system integration. Scaling of System on Chip (SoC) alone does not address today's requirements in terms of performance, functionality, miniaturization, low production cost and time to market of smart electronic system. The traditional microelectronic packaging will more and more convert into complex system integration. ""More than Moore"" will be required due to tighter integration of system level components at the package level. This trend leads to advanced System in Package solutions (SiP) which require the synergy and a combination of wafer level and board integration technologies and which are rapidly evolving from a specialty technology used in a narrow set of applications to a high volume technology with wide ranging impact on electronics markets especially due to the high volume and very cost competitive consumer and communication market. Advanced SiP approaches explore the third dimension which results in complex system architectures that also require, beside new technologies and improved materials, adequate system design tools and reliability models. One of the most promising technology approaches is 3D packaging which involves a set of different integration approaches including stacked packages, silicon interposer with Through Silicon Vias (TSV) and embedding technologies. The paper highlights future system and potential technical solutions.
  • Publication
    From packaging to system integration - the paradigm shift in microelectronics
    ( 2004)
    Wolf, M.J.
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    Reichl, H.
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    Adams, J.
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    Aschenbrenner, R.
    Faced with the rapid development of IC technology the traditional packaging is merging into a complex system integration technique to satisfy the growing demand in terms of increased functionality, performance and miniaturization of electronic products. This requires the development of new packaging and system integration technologies using complex design tools along with new materials to realize complex systems in a package carrying multiple components such as silicon ICs, MEMS, sensors or optical devices. Some major aspects, challenges and requirements of system integration technologies are discussed which will be of special interest in the next years.
  • Publication
    Reliability investigations of hard core solder bumps using mechanical palladium bumps and SnPb solder
    ( 2002)
    Oppermann, H.
    ;
    Kalicki, R.
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    Anhöck, S.
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    Kallmayer, C.
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    Klein, M.
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    Aschenbrenner, R.
    ;
    Reichl, H.
    The choice of solder joint metallurgy is a key issue especially for the reliability of flip-chip assemblies. Besides the metallurgical systems already widely used and well understood, new materials are emerging as solderable under bump metallization (UBM). For single chip bumping Pd stud bumps form a solid core under the solder layer. These hard core solder bumps are an adequate solution if single dies are available only and the chosen assembly technology is flip chip soldering. The scope of this paper is to summarize the results from aging of lead/tin solder bumps on Palladium. The growth of intermetallic and its impact on the mechanical reliability are investigated.
  • Publication
    Pb-free Sn/3.5Ag electroplating bumping process and under bump metallization (UBM)
    ( 2002)
    Jang, S.Y.
    ;
    Wolf, J.
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    Ehrmann, O.
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    Gloor, H.
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    Reichl, H.
    ;
    Paik, K.W.
    Pb-free solder is one of the biggest issues in today's electronic packaging industry. This paper introduces a newly developed Sn/3.5Ag alloy plating process For wafer level bumping. The effects of Under Bump Metallization (UBM) on the process, interfacial reaction, and mechanical strength have been investigated. Four different types of sputtering-based UBM layers-TiW/Cu/electroplated Cu, Cr/CrCu/Cu, NiV/Cu, and TiW/NiV-were fabricated with eutectic Pb/63Sn and Sn/3.5Ag solder. The result shows that the Sn/Ag solder gains Cu or Ni from UBM's and becomes Sn/Ag/Cu or Sn/Ag/Ni during reflow process. Sn/Ag solder has higher reactivity with Cu and Ni than Pb/63Sn. The Intermetallic Compound (IMC) spalling from the interface between UBM/solder has been observed on Cr/CrCu/Cu and TiW/NiV UBM's. However, the IMC spalling phenomena did not decrease the bump shear strength with a bump size of 110 mum, whereas a size of 60 pm brought a decrease in shear value and failure mode change.