Fraunhofer-Institut für Zuverlässigkeit und Mikrointegration IZM

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  • Publication
    Modeling and optimization of bond wires as transmission lines and integrated antennas at RF/microwave frequencies
    ( 2011)
    Ndip, I.
    ;
    Tschoban, C.
    ;
    Schmitz, S.
    ;
    Ostmann, A.
    ;
    Schneider-Ramelow, M.
    ;
    Guttowski, S.
    ;
    Reichl, H.
    ;
    Lang, K.-D.
    In this contribution, the authors present a systematic approach for optimizing the RF performance of bond wires. First of all, a comparative analysis between two of the most commonly used bond wire signal configurations, the two conductor and coplanar configurations, is done. Their results reveal that although the partial self-inductance of the signal wires is the same in both configurations, the partial mutual inductance of the coplanar configuration is higher, resulting in a smaller loop inductance. Consequently, the return and insertion losses are smaller. By reducing the distance between the signal and return currents, they further reduced the loop inductance, and significantly optimized the coplanar configuration. For example, considering a 1 mm long bond wire with a diameter of 25 micron, they successfully kept the power lost through the coplanar configuration below 10 % at 15 GHz, in comparison to the 70 % power lost through the two-conductor configuration at the same frequency. However, more than 30 % of the entire power is lost through the optimized coplanar configuration at 40 GHz. At such frequencies where bond wires are unsuitable to be used as transmission lines, they demonstrate that they are very efficient as antennas by designing a half-loop integrated bond wire antenna having a bandwidth of 3 GHz. For experimental verification, test samples were designed, fabricated and measured. An excellent correlation was obtained between simulation and measurement.
  • Publication
    Large area embedding for heterogeneous system integration
    ( 2010)
    Braun, T.
    ;
    Becker, K.-F.
    ;
    Böttcher, L.
    ;
    Bauer, J.
    ;
    Thomas, T.
    ;
    Koch, M.
    ;
    Kahle, R.
    ;
    Ostmann, A.
    ;
    Aschenbrenner, R.
    ;
    Reichl, H.
    ;
    Bründel, M.
    ;
    Haag, J.F.
    ;
    Scholz, U.
    The constant drive to further miniaturization and heterogeneous system integration leads to a need for new packaging technologies which also allow large area processing with potential for low cost applications. Wafer level embedding technologies and embedding of active components into printed circuit boards CChip-in-Polymer) are two major packaging trends in this area. This paper describes the use of compression and transfer molding techniques for multi chip embedding in combination with large area and low cost redistribution technology from printed circuit board manufacturing as adapted for Chip-in-Polymer applications. The work presented is part of the German governmental funded project SmartSense. Embedding by transfer molding is a well known process for component embedding that is widely used for high reliable microelectronics encapsulation. However, due to material flow restrictions transfer molding does not allow large area encapsulation, but offers a cost effecti ve technology for embedding on a medium size scale as known e.g. from MAP Cmolded array packaging) molding Ctypically with sizes up to 60×60 mm2). In contrast, compression molding is a relatively new technology that has been especially developed for large area embedding of single chips but also of multiple chips or heterogeneous systems on wafer scale, typically up to 8" or even up to 12". Wiring of these embedded components is done using PCB manufacturing technologies, i.e. a resin coated copper CRCC) film is laminated over the embedded components - no matter which shape the embedded components areas are: a compression molded wafer, larger rectangular areas or smaller transfer molded systems CMAP). Typical process flow for RCC redistribution is lamination of RCC, via drilling to die pads by laser, galvanic Cu via filling, conductor line and pad formation by Cu etching, soldermask and solderable surface finish application - all of them standard PCB processes. The feasibility of the technology is dem
  • Publication
    Chip embedding technology developments leading to the emergence of miniaturized system-in-packages
    ( 2010)
    Manessis, D.
    ;
    Boettcher, L.
    ;
    Ostmann, A.
    ;
    Aschenbrenner, R.
    ;
    Reichl, H.
    At PCB manufacturing level, 50 m thin chips have been embedded with pitches up to 200 m in up to 18"×24" panels. This paper shows the further developments in chip embedding technologies to incorporate chips with even smaller pitches. The technology developed in this study does not necessitate expensive redistribution layers for enlarging the pad pitch. Embedding of small pitch chips has been realised with concurrent developments in accurate chip positioning, plating methods and chemistries and ultra fine line patterning. The results in this paper show the emergence of a new prototype Embedded chip-QFN package with contact pads at 400m pitch and a total number of 84I/Os with dimensions of 10mm×10mm. The embedded chip in the QFN package is 5mm×5mm in size and has a peripheral pad configuration at 100m pitch. All Embedded chip-QFN packages have been manufactured in 10"×14" panels at prototype level. This paper also addresses all challenges for semi-additive processes for c opper structuring of chip embedded packages with pitches lower than 100m. Qualitative analysis using acoustic microscopy and shear testing of the QFNs provides evidence of good resin adhesion and package mechanical robustness. This study shows promising results for embedding of chips with different contact pitches through alternative embedding strategies and in conjunction with developments for very dense copper routing, it provides strong evidence for the manufacturability of highly miniaturised embedded chip system-in-packages with a total thickness of 160m.
  • Publication
    Stretchable circuit board technology in textile applications
    ( 2009)
    Ostmann, A.
    ;
    Vieroth, R.
    ;
    Seckel, M.
    ;
    Löher, T.
    ;
    Reichl, H.
    Today's electronic systems are based on an assembly of components onto rigid or flexible substrates, serving perfectly the needs of traditional product fields like automotive, computing or industry electronics. On the other hand, many of the demands from emerging applications like wearable and textile electronics cannot be met if standard technologies are used for their realization. These new fields have therefore become mayor drivers for the development of novel technologies. Among these 'stretchable electronics' have attracted strong attention. Especially for textile applications the potential of electronic systems to comply with the body shape and movement will improve the user comfort dramatically. A manufacturing technology for the realization of stretchable systems by common printed circuit board techniques, based on polyurethane as a stretchable matrix material has been developed. The stretchable circuit board technology has been used to realize a number of texti le applications. As an example the realization of a fashion dress with integrated high brightness LEDs and movement sensing will be described.
  • Publication
    Advancements in bumping technologies for flip chip and WLCSP packaging
    ( 2009)
    Manessis, D.
    ;
    Patzelt, R.
    ;
    Ostmann, A.
    ;
    Reichl, H.
    At R&D level, IZM has advanced stencil printing very close to its technological limits at pitches even down to 50 mum. Innovative electroformed and laser-cut with nano-treatment stencils have been manufactured with an extreme thinness of 20 mum for bumping wafers at ultra fine pitches (UFP) of 100 mum, 80 mum and 60 mum. Specifically, for 100 mum pitch bumping, both type 7 (2-11 mum) and type 6 (5-15 mum) pastes of eutectic composition Sn63/Pb37 have been successfully employed. Bumping using 25 mum electroformed stencil thickness has yielded bump heights of 42.3plusmn3.8 mum and 43.6plusmn3.5 mum for type 7 and type 6 pastes, respectively. A newly prototype developed type 8 paste (2-8 mum) has been used for the first time to bump chips with peripheral contacts at 80 mum and 60 mum pitch. Bumping at 80 mum pitch with nano-treated laser-cut stencil has yielded bumps of 28 mum in height. For bumping at 60 mum pitch, a 20 mum thick electroformed stencil was used with 35 mum times 80 mum oblong apertures. Printing at 60 mum pitch has yielded very promising results and has proved the capability of electroformed technology to manufacture accurate and robust thin stencils. The bump height at 60 mum pitch was measured to be 28 plusmn3 mum. Paste-in-resist technology has been developed as an alternative to stencils in order to overcome the manufacturing difficulties of making extremely small apertures. Paste is printed in resist apertures which have been opened by photolithographic processes. In this way, bumping has been demonstrated up to 50 mum pitches. Complimentary to stencil printing processes, IZM has developed balling technologies up to 400 mum pitch up to 8rdquo wafers with a thickness of 150 mum. Solder balling can be achieved either by ldquoperform ball printrdquo using conventional stencil printers with specially designed stencils or by ldquoball droprdquo techniques. Balling technologies have demonstrated the application of 300 mum and 250 mum Sn-Pb and Pb-f- ree balls at respective area array pitches of 500 mum and 400 mum, the main I/O pitches for WL-CSP bumping.
  • Publication
    Innovative package realization by Chip Embedding Technologies
    ( 2009)
    Böttcher, L.
    ;
    Manessis, D.
    ;
    Karaszkiewicz, S.
    ;
    Ostmann, A.
    ;
    Reichl, H.
    The chip embedding technology achieved significant progress the last years. After various research activities the main focus is today on industrialization and implementation of new business models. In the project HERMES European partners from industry and research aim to bring embedding technology based on low-cost PCB /Printed Circuit Board) processes to a market-ready product flow, demonstrated by automotive, power electronics and telecommunication applications. The research part of the project aims to overcome current limitations and to achieve even higher levels of miniaturisation. This paper will describe the embedding process flow and will discuss the process steps in detail. An embedded QFN (Quad Flat No-Lead) package will be described and discussed. Especially the realisation of the QFN is a strong challenge for today's machine capabilities, since it contains a chip with a pitch of 100 µm.
  • Publication
    Stretchable electronic systems: Realization and applications
    ( 2009)
    Löher, T.
    ;
    Seckel, M.
    ;
    Vieroth, R.
    ;
    Dils, C.
    ;
    Kallmayer, C.
    ;
    Ostmann, A.
    ;
    Aschenbrenner, R.
    ;
    Reichl, H.
    Commonplace electronic appliances for consumer or industrial use are still mostly rigid or at maximum flexible entities. The flexibility of foldable units like laptops or cell phones is usually realized through flexible circuit board (FCB) interconnectors. Although flexibility allows for considerably enhanced degrees of freedom in design, it is not compatible with more complex three dimensional curvatures and dynamics thereof. In the past years a number or approaches to realize stretchable electronic circuits in order to reach beyond unidirectional bending or folding of electronics have been reported. In the frame of the European Project STELLA a particular fabrication technology for stretchable electronic systems has been developed at Technische Universitaet Berlin. This technology, termed "stretchable circuit board" (SCB) technology, is derived from conventional printed circuit board manufacturing. Stretchability of the boards is enabled by (i) using polyurethane inst ead of FR4 or polyimide as a carrier material of the copper structures and (ii) a meandering design of the Cu interconnects between commercial (rigid) electronic components. Such boards can be (once) extended by up to 300 % before fracture of the Cu interconnections. For repeated elongation/relaxation cycles elongations with a few percent are allowable in order reach high cycle numbers. Electronic components are assembled after local application of a solder mask and surface finish for solderability. The electronic interconnection is established using a low temperature solder alloy (SnBi, Tm=142 °C). For protection and enhanced system robustness all components are subsequently encapsulated within a polyurethane capping. Systems thus realized can be readily attached to different kinds of surfaces. Most interesting for various application cases is the easy attachment to textile substrates by a simple lamination process. The field use case studies of stretchable systems in the frame of the STELLA are mo
  • Publication
    Innovative approaches for realisation of embedded chip packages - technological challenges and achievements
    ( 2009)
    Manessis, D.
    ;
    Böttcher, L.
    ;
    Ostmann, A.
    ;
    Aschenbrenner, R.
    ;
    Reichl, H.
  • Publication
    Electrical design and characterization of elevated antennas at PCB-level
    ( 2009)
    Ohnimus, F.
    ;
    Podlasly, A.
    ;
    Bauer, J.
    ;
    Ostmann, A.
    ;
    Ndip, I.
    ;
    Guttowski, S.
    ;
    Reichl, H.
    In this work, elevated microstrip patch antennas are designed and characterized at quasi millimeter-wave frequencies. Radiation efficiencies of up to 83% are reported at 24 GHz. The designed circular and rectangular patch antennas are fed through impedance controlled microstrip lines by means of proximity coupling. The elevated patches are supported by conventional vias. The proposed layer build-up comprises a low cost board substrate, a low loss 100 mum-thick prepreg layer and an elevated copper layer. The fabrication of the antennas is particularly favourable because the structures are manufactured with typical PCB manufacturing processes like copper plating, etching, resist lamination and laser drilling. This allows the manufacturing of many structures on large area panels.
  • Publication
    Embedding technology development for a 77 GHz automotive radar system
    ( 2009)
    Becker, Karl-Friedrich
    ;
    Koch, M.
    ;
    Kahle, R.
    ;
    Braun, T.
    ;
    Böttcher, L.
    ;
    Ostmann, A.
    ;
    Kostelnik, J.
    ;
    Ebling, F.
    ;
    Noack, E.
    ;
    Sommer, J.P.
    ;
    Richter, M.
    ;
    Schneider, M.
    ;
    Reichl, H.
    Radar sensors are already employed in production model vehicles e.g. for adaptive cruise control (ACC) systems. Further development of driver assistance systems has also led to the use of radar sensors in active safety systems (active brake assistance, collision warning, emergency braking, etc). However, the costs of manufacturing such radar-based systems, capable of gathering reliable information from surroundings, for vehicles across the market spectrum or for compact executive cars are still too high. Thus, despite the improved reliability characteristics, detection properties and safety required for these sensors, the aim is to manufacture such systems more cost-effectively. The German national ""KRAFAS (Cost-optimized Radar Sensor for Active Driver Assistance Systems)"" project is aiming at integrating 77 GHz components (esp. SiGe MMICs) into a printed circuit board, combining driver and 77 GHz RF circuitry and integrating antenna elements. This will significantly reduce current costs of the 77 GHz RF module by 20-30%. In this paper, design, simulation, technological development, realization and subsequent measurement of interconnects of embedded active 77 GHz chips to a high frequency substrate using microvia technology are described. The used molded embedding technology offers great opportunities for a very broad range of frequencies and applications as well as large potential for cost reduction.