Fraunhofer-Institut für Zuverlässigkeit und Mikrointegration IZM

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Angle-of-attack investigation of pin-fin arrays in nonuniform heat-removal cavities for interlayer cooled chip stacks

2011 , Brunschwiler, T. , Paredes, S. , Drechsler, U. , Michel, B. , Wunderle, B. , Reichl, H.

Interlayer cooling removes the heat dissipated by vertically stacked chips in multiple integrated fluid cavities. Its performance scales with the number of dies in the stack and is therefore superior to traditional back-side heat removal. Previous work indicated that pin-fin arrays are ideally suited as through-silicon-via-compatible heat transfer structures. In addition, four-port fluid-delivery and fluid-guiding structures improve the heat-removal performance for the nonuniform power maps of high-performance microprocessor chip stacks. Accordingly, an extension of the porous-media multi-scale modeling approach is presented as an efficient approach for designing nonuniform heat transfer cavities. A tensor description in combination with a look-up table is proposed to physically describe periodic porous media, such as pin-fin arrays, in detail. Conjugate heat and mass transfer sub-domain modeling is performed with periodic boundary conditions to derive the orientation-d ependent permeability and angle offset between the pressure gradient and the Darcy velocity direction for pin-fin arrays with a pin diameter of 50 m and pitch and height of 100 m. A local permeability minimum at a flow direction of approx. 30° could be identified. At higher velocities, the fluid flow is biased towards the symmetry lines of the pin-fin array. The modeling concept was validated with experimental readings of a nonuniform, double-side-heated single test cavity. The main characteristics of the temperature field with respect to the four-port architecture, the guiding structures, the fluid temperature increase, and the nonuniform power dissipation are predicted correctly. A statistical comparison of power maps with different heat transfer contrast values resulted in a mean accuracy <6% at a maximal standard deviation of 22.2%. Finally, the potential of the four-port architecture for nonuniform power maps with hot spots in the corners was demonstrated.

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Advances in thermal interface technology: Mono-metal interconnect formation, processing and characterisation

2010 , Wunderle, B. , Klein, M. , Dietrich, L. , Abo Ras, M. , Mrossko, R. , May, D. , Schacht, R. , Oppermann, H. , Michel, B. , Reichl, H.

As the demand for new thermal technologies and materials has been increasing over the years to provide thermal solutions to the next generation of power electronics, microprocessors and high-power optical systems also thermal characterisation methods have to keep up with the pace of this development with respect to resolution and accuracy. We have developed both bulk and interface technologies to reduce thermal resistance using Ag and Au-based materials and low-T and low-p processes to render them eligible for the electronics industry. New processes to generate nano-enhanced surface structures as well as thermo-compression bonding are examined within this paper. Along with these processes especially designed test stands are described which are able to extract the effects achieved by the technological advances.

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Hotspot-optimized interlayer cooling in vertically integrated packages

2009 , Brunschwiler, T. , Michel, B. , Rothuizen, H. , Kloter, U. , Wunderle, B. , Reichl, H.

High-performance, vertically integrated chip stacks with multiple logic layers and aligned hot spots, need cooling by an interlayer heat-removal approach. At high interconnect densities, fluid friction increases dramatically, and the most significant portion of the junction temperature rise is due to a sensible heat increase in the fluid. First we introduce three building blocks that extend the interlayer cooling capability to an interconnect pitch less than 100m by considering hot-spot-aware mass and heat transfer. The methods used are hydraulic diameter modulation, four-port fluid access, and fluid focusing. Second, we demonstrate an approach to combine these methods based on an efficient porous-medium approach using expressions for pressure gradients and convective thermal resistances derived from detailed sub-modeling in communicating pin fin array cavities. Finally, three different global heat-transfer layouts are compared.

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Molecular dynamics approach to structure-property correlation in epoxy resins for thermo-mechanical lifetime modeling

2009 , Wunderle, B. , Dermitzaki, E. , Hölck, O. , Bauer, J. , Walter, H. , Shaik, Q. , Rätzke, K. , Faupel, F. , Michel, B. , Reichl, H.

This paper addresses the potential of molecular dynamics simulation for structure-property correlations in epoxy-resins. This is an important topic within a multi-scale framework to lifetime prediction in electronic packaging. For that purpose, epoxy-resins with small systematic variations in chemical structure have been synthesised and then characterised by various thermo-mechanical testing methods. It was found that moisture diffusion showed the greatest response with respect to material and loading parameters such as polarity, free volume, moisture concentration and temperature. Based on a parametric study, modeling approaches of various complexity have been able to show first qualitative but then also quantitative agreement. The paper comments further on the accuracy and limits of the method and correlates the calculations with experimental structural analysis results.

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Molecular dynamics approach to structure-property correlation in epoxy resins for thermo-mechanical lifetime modeling

2010 , Wunderle, B. , Dermitzaki, E. , Hölck, O. , Bauer, J. , Walter, H. , Shaik, Q. , Rätzke, K. , Faupel, F. , Michel, B. , Reichl, H.

This paper addresses the potential of molecular dynamics simulation for structureproperty correlations in epoxy-resins. This is an important topic within a multi-scale framework to lifetime prediction in electronic packaging. For that purpose, epoxy-resins with small systematic variations in chemical structure have been synthesised and then characterised by various thermo-mechanical testing methods. It was found that moisture diffusion showed the greatest response with respect to material and loading parameters such as polarity, free volume, moisture concentration and temperature. Based on a parametric study, modeling approaches of various complexity have been able to show first qualitative but then also quantitative agreement. The paper comments further on the accuracy and limits of the method and correlates the calculations with experimental structural analysis results.

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Heat-removal performance scaling of interlayer cooled chip stacks

2010 , Brunschwiler, T. , Paredes, S. , Drechsler, U. , Michel, B. , Cesar, W. , Leblebici, Y. , Wunderle, B. , Reichl, H.

Interlayer cooling is the only heat removal concept which scales with the number of active tiers in a vertically integrated chip stack. In this work, we numerically and experimentally characterize the performance of a three tier chip stack with a footprint of 1cm2. The implementation of 100m pitch area array interconnect compatible heat transfer structures results in a maximal junction temperature increase of 54.7K at 1bar pressure drop with water as coolant for 250W/cm2 hot-spot and 50W/cm2 background heat flux. The total power removed was 390W which corresponds to a 3.9kW/cm 3 volumetric heat flow. An efficient multi-scale modeling approach is proposed to predict the temperature response in the complete chip stack. The experimental validation confirmed an accuracy of +/- 10%. Detailed sub-domain modeling with parameter extraction is the base for the system level porous-media calculations with thermal field-coupling between solid - fluid and solid - solid interfaces. F urthermore, the strength and weakness of microchannel and pin fin heat transfer geometries in 2-port and 4-port fluid architectures is identified. Microchannels efficiently mitigate hot spots by distributing the dissipated heat to multiple cavities due to their low porosity. Pin fins with improved permeability and convective heat dissipation are advantageous at small power map contrast and aligned hot spots on the different tiers. Large stacks of 4cm2 can be cooled sufficiently by the 4-port fluid delivery architecture. The flow rate is improved four times compared to the 2-port fluid manifold. The non-uniformity of the flow in case of the 4-port demands a more careful floor-planning. Furthermore optimization schemes such as hot-spot distribution, individual hot-spot heat flux adjustment, as well as hot-spot sub-millimeter dimensioning to minimize pumping power and maximize chip stack performance are proposed.

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Thermo-mechanical reliability during technology development of power chip-on-board assemblies with encapsulation

2009 , Wunderle, B. , Becker, K.-F. , Sinning, R. , Wittler, O. , Schacht, R. , Walter, H. , Schneider-Ramelow, M. , Halser, K. , Simper, N. , Michel, B. , Reichl, H.

In this paper we examine the thermo-mechanical reliability of polymer-encapsulated chip-on-board (COB) assemblies for power applications by simulation and experiment. Thereby the focus is set on the low cycle fatigue failure behaviour of the die-attach material under thermal cycling conditions. As die-attach material different solder materials and Ag-filled thermal adhesives have been used. The encapsulation was performed with a soft silicone-based and hard silica-reinforced epoxy-based material, respectively. An other process variable takes into account die-tilt. The study was carried out as a feasibility analysis in the course of a COB technology development. To this end lifetime models have been employed to correlate crack growth in the, i.e. attach to a computational accumulative failure criterion which allows to consistently describe ad predict quantitatively the lifetime of the assemblies. Thereby a considerable influence of the encapsulation was found. In particular it could be shown that a hard encapsulation largely increases reliability for solder die-attach.

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Molecular modeling of a 3D-crosslinked epoxy resin and its interface to native SiO2 - property prediction in microelectronic packaging

2010 , Hölck, O. , Dermitzaki, E. , Wunderle, B. , Bauer, J. , Michel, B. , Reichl, H.

In this paper first results are presented on the construction and property estimation of 3D networked epoxy molding compounds by molecular dynamics simulations. Our investigations present part of general trend to extend failure analysis, reliability assessment and the development of packaging materials from the conventional discrete usage of simulation techniques to a more holistic approach of an interconnected multimethods-procedure, enabling bottom-up simulation of complex microsystems. Within such a scheme of research, methods of detailed atomistic molecular modeling need to be developed in order to take materials development as well as materials failure analysis to the nanoscale level. In this work we present a crosslinking scheme for the construction of truly three dimensionally crosslinked simulation packages and report a first property analysis of this molding compound material. The challenge of atomistically describing ideal interfaces of crosslinked epoxies to an amorphous silicon-dioxide surface is tackled and first models and results are presented.

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Zerstörungsfreie Beobachtung von Rissen in Leiterplattendurchkontaktierungen - Quantisierung der Risslänge mittels Impulsthermographie und FEM-Simulation

2010 , Schacht, R. , Abo Ras, M. , May, D. , Wunderle, B. , Michel, B. , Reichl, H.

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Nondestructive failure analysis and simulation of encapsulated 0402 multilayer ceramic chip capacitors under thermal and mechanical loading

2009 , Wunderle, B. , Braun, T. , May, D. , Michel, B. , Reichl, H.

The use of multilayer ceramic chip capacitors as integrated passive in, e.g., system in package applications needs methods to examine and predict their reliability. Therefore, a nondestructive failure analytical technique is described to detect cracks in the ceramic and the metallic layers within encapsulated 0402 surface mount device (SMD) capacitors. After choosing from techniques to reproducibly generate cracks, it is shown that an in situ capacitance measurement is a convenient method to detect these failures unambiguously. Finite element simulations support the experimental results. A reliability estimate for capacitor integrity under given loading conditions is given.

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