Fraunhofer-Institut für Zuverlässigkeit und Mikrointegration IZM

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Fan-Out Wafer and Panel Level Packaging - A Platform for 3D Integration

2021 , Braun, T. , Becker, K.-F. , Töpper, M. , Aschenbrenner, R. , Schneider-Ramelow, M.

The constant drive to further miniaturization and heterogeneous system integration leads to a need for new packaging technologies that also allow large area processing and 3D integration with strong potential for low cost applications. Here, Fan-Out Wafer Level Packaging [FOWLP] is one of the latest packaging trends in microelectronics. The technology can be also used for multi-chip packages or System in Package (SiP). 3D integration is typically done by package on package (PoP) stacking where the electrical 3D routing is done by through mold (TMV) or through package vias (TPV) and a redistribution layer on both sides of the FOWLP. In summary the paper will give a review of the different technology approaches for through mold vias in a Fan-out Wafer or Panel Level Package.

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Panel Level Packaging for Component Integration of an Energy Harvesting System

2019 , Braun, T. , Kahle, R. , Voges, S. , Hölck, O. , Bauer, J. , Becker, K.-F. , Aschenbrenner, R. , Dreissigacker, M. , Schneider-Ramelow, M. , Lang, K.-D.

Within the European funded project smart-MEMPHIS the goal was to tackle the main challenge for all smart devices - self-powering. The project was aimed to design, manufacture and test a miniaturized autonomous energy supply based on harvesting vibrational energy with piezo-MEMS energy harvesters. Cost effective packaging was needed for 3D system integration of a MEMS-based multi-axis energy harvester, an ultra-low-power ASIC to manage the variations of the frequency and harvested power, and a miniaturized energy storing supercapacitor. Miniaturization was another key demand as target applications were a leadless pacemaker and a wireless sensor network for structural health monitoring. Panel Level Packaging (PLP) was selected as packaging technology for the harvester components. A basic study on the embedding of piezo-MEMS harvester has been performed as well as the development and proof of concept of a new PLP based supercapacitor housing. For the power management unit an ASIC together with two capacitors have been integrated by Fan-out Panel Level Packaging (FOPLP). Material selection and process development was first done on wafer level size and then transferred to large area 457×305 mm 2 panel size. Main focus was here to find a suitable material combination and process parameters for the embedding of SMD capacitors together with bare dies in a fan-out panel level package. A technology study has been performed to analyze the influence of SMD component size and pitch, thermal release tape and epoxy molding compound type during compression molding. Results have used to finally select materials for prototype built. Reliability testing have been performed to prove the overall concept and material selection for PLP.

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Numerische und experimentelle Betrachtung des Molded Underfills

2019 , Paetsch, M. , Nguyen, T.D. , Dreissigacker, M. , Bauer, J. , Hoelck, O. , Bader, V. , Braun, T. , Zuehlke, J. , Minkus, M. , Voges, S. , Becker, K.-F. , Woehrmann, M. , Lang, K.-D. , Schubert, D.W. , Schneider-Ramelow, M.

Zum Schutz vor thermischer und mechanischer Beanspruchung durch verschiedenste Umweltfaktoren werden Flip Chips verkapselt, um eine zuverlässige Funktionsweise zu gewährleisten. Dazu werden typischerweise niederviskose Polymere auf Epoxidbasis eingesetzt. Die klassische Verkapselung mittels Capillary Underfill (CUF) erfolgt innerhalb zweier Prozessschritte. Den sogenannten Underfill, bei dem das Material durch Kapillarkräfte getrieben unter den Chip fließt. Dieser Prozessschritt ist besonders zeitintensiv und verhindert einen hohen Durchsatz. Anschließend erfolgt eine Nachverkapselung mittels Overmolding durch Transfer- oder Formpressen. Vakuum-unterstütztes Formpressen ermöglicht ein vollständiges, simultanes Underfillen und Übermolden innerhalb eines Prozessschrittes. Eine Implementation des Molded Underfills (MUF) benötigt lediglich eine Produktionsmaschine, reduziert Materialkosten, Prozesszeiten und ermöglicht höhere Durchsätze. Ein besonderer Vorteil liegt darin, dass keine neue Infrastruktur geschaffen werden muss und dass nur minimale Investitionen bei der Umstellung notwendig sind. Bei MUF-Prozessen wird ein Substrat mit den zu verkapselnden Chips in die Kavität eingelegt und anschließend verschlossen. Nachdem eine gewünschte Güte des Vakuums erreicht ist, fährt die Presse auf die Endposition und verpresst das Epoxy Molding Compound (EMC) in die Kavitäten ober- und unterhalb der Chips. Nach kurzem Vorhärten des EMC im Moldwerkzeug kann das Substrat aus dem dann geöffneten Werkzeug entnommen werden. Eine Problematik, die auch ähnlich bei dem klassischen Underfill auftritt, ist die Entstehung von Fehlstellen, d.h. von Lufteinschlüssen (Voids) im Spalt zwischen Chip und Substrat, die Zuverlässigkeitsreduzierend wirken können. Die Auswirkungen der Variation von Prozess- und Geometrieparametern im Moldprozess auf die Entstehung dieser Lufteinschlüsse, sind zumeist nur grob qualitativ beschrieben, quantitative Beschreibungen sind nicht publiziert. Mit Hilfe eines numerischen Modells, welches die spezifischen Materialeigenschaften des EMCs berücksichtigt, konnte ein grundlegendes Verständnis für das Fließen des Materials geschaffen, sowie eine Vorauswahl an Parameter getroffen werden. Dies lieferte wertvolle Einblicke in das Fließverhalten, die experimentell unter diesen Voraussetzungen nicht zugänglich sind. Das zu füllende Volumen entscheidend für die Form der Fließfront. Eine Vielzahl an Chipgeometrien, Bumphöhen und Packagedicken wurden in dieser Arbeit unter Nutzung realistischer Prozessparameter auf ihre Eignung für den MUF analysiert und bewertet. Durch die hier erarbeiteten Ergebnisse ist es möglich, erste Hinweise zu geben, unter welchen Randbedingungen der Einsatz des MUF zu einem gewünschten Ergebnis führt und birgt somit nicht nur das Potential in Zukunft weiter an Bedeutung zu gewinnen, sondern auch langfristig enormen Aufwand und Kosten einzusparen.

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Die Realisierung von Umverdrahtungslagen mittels Inkjet-Printing im Fan-Out Wafer Level Packaging

2019 , Dreissigacker, M. , Roshanghias, A. , Becker, K.-F. , Braun, T. , Schneider-Ramelow, M. , Lang, K.D.

Beim Fan-Out Wafer- und Fan-Out Panel-Level Packaging (FOWLP/FOPLP) zur Heterogensystemintegration mikroelektronischer Baugruppen werden elektrische Umverdrahtungslagen (Redistribution Layers, RDLs) zur elektrischen Verbindung zwischen den Komponenten benötigt. Diese werden meist mittels einer Kombination von Photolithographie und nasschemischen Methoden erzeugt. Der Einsatz additiver Fertigungstechnologien (z.B. Drucken funktionaler Materialien im Inkjet-Verfahren) erfährt hierbei in der letzten Zeit mehr Beachtung. Dabei wird - im Gegensatz zu subtraktiven Methoden, wie die der Photolithographie - nur dort Material aufgebracht, wo es benötigt wird. Weiterhin bringen flächige Umverdrahtungslagen durch die großen Unterschiede der thermischen Ausdehnungskoeffizienten (coefficient of thermal expansion, CTE) Stress in das Package, welcher sich dann in Form von Verbiegung und letztendlich verkürzter Lebensdauer äußert. Für MEMS mit sensiblen Membranen ist dieser Ansatz, besonders im Kontext von FOWLP-Fertigungsprozessen, vielversprechend, da hierbei der eventuelle Einsatz von temporären Opferschichten vermieden werden kann und durch eine vereinfachte Prozesskette, sowie geringeren Materialverbrauch, Zeit und Kosten eingespart werden können. Der Prozessfluss wird am Beispiel von Drucksensoren bzw. Mikrophonen demonstriert, es wird auf potenziell kritische Stellen eingegangen. Ein Schwerpunkt hierbei ist die Oberflächenstruktur der zu bedruckenden Oberfläche, welche Einfluss auf die minimale Strukturbreite der gedruckten Leiterbahnen hat. Weiterhin werden Stufen zwischen Chips und Substratoberfläche diskutiert.

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Simulation challenges of warpage for wafer- and panel level packaging

2020 , Dijk, M. van , Kuttler, S. , Rost, F. , Jeaschke, J. , Walter, H. , Wittler, O. , Braun, T. , Schneider-Ramelow, M.

Fan-out Wafer and panel level packaging is one of the latest trends in microelectronic packaging. Realizing System in Packages (SiP) by wafer- or panel-level packaging, using overmolding and redistribution layers, requires several processing steps which all lead to different stress states in the panel/wafer assembly. These stresses result in deformation of the panel/wafer, so called warpage. Keeping the warpage within limits is important as subsequent processing steps can fail if deformations are too large or at least influences the reliability of the final SiP.Many experimental results have shown that the deformation is mostly non-symmetrical, meaning that instead of a symmetrical - bowl shaped deformation - a tunnel shaped deformation occurs. The main focus of this study is on how to represent this non-symmetrical deformation with numerical simulations. Our results show that the release step of the temporary carrier, necessary to hold the dies and mold compound during the processing, has a strong influence on the warpage, and needs to be considered to represent the warpage correctly.

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Panel Level Packaging - From Idea to Industrialization -

2019 , Braun, T. , Becker, K.-F. , Hoelck, O. , Voges, S. , Boettcher, L. , Töpper, M. , Stobbe, L. , Aschenbrenner, R. , Voitel, M. , Schneider-Ramelow, M. , Lang, K.-D.

Drivers for 3D packaging solutions are manifold and each requirement calls for different answers and technologies. Main goal is miniaturization, but component density and performance, simplification of design and assembly, flexibility, functionality and finally, cost and time-to-market have been found to be the core drivers for going 3D as well. Besides die and package stacking, embedding dies is a key technology for heterogeneous system integration. There are two main approaches for embedded die technologies: Fan-out Wafer and Panel Level integration, where dies are embedded into polymer encapsulants and Chip in Polymer, where dies are embedded into the substrate.

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Where is the Sweet Spot for Panel Level Packaging?

2019 , Braun, T. , Becker, K.F. , Hölck, O. , Voges, S. , Wöhrmann, M. , Böttcher, L. , Töpper, M. , Stobbe, L. , Aschenbrenner, R. , Schneider-Ramelow, M. , Lang, K.D.

Fan-out Wafer Level Packaging (FOWLP) is one of the latest packaging trends in microelectronics. Besides technology developments towards heterogeneous integration including multiple die packaging, passive component integration in package and redistribution layer or package-on-package approaches also larger rectangular substrates formats are targeted.

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On the feasibility of fan-out wafer-level packaging of capacitive micromachined ultrasound transducers (CMUT) by using inkjet-printed redistribution layers

2020 , Roshanghias, A. , Dreissigacker, M. , Scherf, C. , Bretthauer, C. , Rauter, L. , Zikulnig, J. , Braun, T. , Becker, K.-F. , Rzepka, S. , Schneider-Ramelow, M.

Fan-out wafer-level packaging (FOWLP) is an interesting platform for Microelectromechanical systems (MEMS) sensor packaging. Employing FOWLP for MEMS sensor packaging has some unique challenges, while some originate merely from the fabrication of redistribution layers (RDL). For instance, it is crucial to protect the delicate structures and fragile membranes during RDL formation. Thus, additive manufacturing (AM) for RDL formation seems to be an auspicious approach, as those challenges are conquered by principle. In this study, by exploiting the benefits of AM, RDLs for fan-out packaging of capacitive micromachined ultrasound transducers (CMUT) were realized via drop-on-demand inkjet printing technology. The long-term reliability of the printed tracks was assessed via temperature cycling tests. The effects of multilayering and implementation of an insulating ramp on the reliability of the conductive tracks were identified. Packaging-induced stresses on CMUT dies were further investigated via laser-Doppler vibrometry (LDV) measurements and the corresponding resonance frequency shift. Conclusively, the bottlenecks of the inkjet-printed RDLs for FOWLP were discussed in detail.

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A numerical study on mitigation of flying dies in compression molding of microelectronic packages

2019 , Dreissigacker, M. , Hoelck, O. , Bauer, J. , Braun, T. , Becker, K.-F. , Schneider-Ramelow, M. , Lang, K.-D.

Compression molding with liquid encapsulants is a crucial process in microelectronic packaging. Material properties of highly filled systems of reactive epoxy molding compounds depend on process conditions in a complex manner, such as shear-thinning behavior, which is superimposed by a time- and temperature-dependent conversion rate, both strongly affecting viscosity. The focus is set on forces exerted on individual dice during encapsulation in fan-out wafer-level packaging (FOWLP). The presented framework consists of an analytical approach to calculate the melt front velocity and simulations carried out to capture the nonlinear kinematics, chemorheology, and to extract forces exerted on individual dice. It offers separate evaluation of pressure and shear contributions for two cases, 0° and 45° between the dice' frontal area and the melt front. Process parameters, such as compression speed, thus cycle time, and process temperature, are determined to keep the forces on the dice below the critical level, where drag forces exceed adhesive forces. As a result, process parameters are determined to minimize flying dice and thereby maximize yield. The approach is easily transferable to arbitrary geometries and is therefore well suited to face the challenges that come with the current efforts toward the transition from FOWLP to larger substrates.

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Fan-Out Wafer and Panel Level Packaging as Packaging Platform for Heterogeneous Integration

2019 , Braun, T. , Becker, K.F. , Hoelck, O. , Voges, S. , Kahle, R. , Dreissigacker, M. , Schneider-Ramelow, M.

Fan-out wafer level packaging (FOWLP) is one of the latest packaging trends in microelectronics. Besides technology developments towards heterogeneous integration, including multiple die packaging, passive component integration in packages and redistribution layers or package-on-package approaches, larger substrate formats are also targeted. Manufacturing is currently done on a wafer level of up to 12/300 mm and 330 mm respectively. For a higher productivity and, consequently, lower costs, larger form factors are introduced. Instead of following the wafer level roadmaps to 450 mm, panel level packaging (PLP) might be the next big step. Both technology approaches offer a lot of opportunities as high miniaturization and are well suited for heterogeneous integration. Hence, FOWLP and PLP are well suited for the packaging of a highly miniaturized energy harvester system consisting of a piezo-based harvester, a power management unit and a supercapacitor for energy storage. In this study, the FOWLP and PLP approaches have been chosen for an application-specific integrated circuit (ASIC) package development with integrated SMD (surface mount device) capacitors. The process developments and the successful overall proof of concept for the packaging approach have been done on a 200 mm wafer size. In a second step, the technology was scaled up to a 457 x 305 mm(2) panel size using the same materials, equipment and process flow, demonstrating the low cost and large area capabilities of the approach.

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