Fraunhofer-Institut für Zuverlässigkeit und Mikrointegration IZM

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  • Publication
    Fan-Out Wafer and Panel Level Packaging - A Platform for 3D Integration
    ( 2021)
    Braun, T.
    ;
    Becker, K.-F.
    ;
    Töpper, M.
    ;
    Aschenbrenner, R.
    ;
    Schneider-Ramelow, M.
    The constant drive to further miniaturization and heterogeneous system integration leads to a need for new packaging technologies that also allow large area processing and 3D integration with strong potential for low cost applications. Here, Fan-Out Wafer Level Packaging [FOWLP] is one of the latest packaging trends in microelectronics. The technology can be also used for multi-chip packages or System in Package (SiP). 3D integration is typically done by package on package (PoP) stacking where the electrical 3D routing is done by through mold (TMV) or through package vias (TPV) and a redistribution layer on both sides of the FOWLP. In summary the paper will give a review of the different technology approaches for through mold vias in a Fan-out Wafer or Panel Level Package.
  • Publication
    Manufacturing of high frequency substrates as software programmable metasurfaces on PCBs with integrated controller nodes
    ( 2020)
    Manessis, D.
    ;
    Seckel, M.
    ;
    Fu, L.
    ;
    Tsilipakos, O.
    ;
    Pitilakis, A.
    ;
    Tasolamprou, A.
    ;
    Kossifos, K.
    ;
    Varnava, G.
    ;
    Liaskos, C.
    ;
    Kafesaki, M.
    ;
    Soukoulis, C.M.
    ;
    Tretyakov, S.
    ;
    Georgiou, J.
    ;
    Ostmann, A.
    ;
    Aschenbrenner, R.
    ;
    Schneider-Ramelow, M.
    ;
    Lang, K.-D.
    The proposed work is performed in the framework of the FET-EU project "VISORSURF", which has undertaken research activities on the emerging concepts of metamaterials that can be software programmable and adapt their properties. In the realm of electromagnetism (EM), the field of metasurfaces (MSF) has reached significant breakthroughs in correlating the micro- or nano-structure of artificial planar materials to their end properties. MSFs exhibit physical properties not found in nature, such as negative or smaller-than-unity refraction index, allowing for EM cloaking of objects, reflection cancellation from a given surface and EM energy concentration in as-tight-as-possible spaces.The VISORSURF main objective is the development of a hardware platform, the Hypersurface, whose electromagnetic behavior can be defined programmatically. The key enablers for this are the metasurfaces whose electromagnetic properties depend on their internal structure. The Hypersurface hardware platform will be a 4-layer build-up of high frequency PCB substrate materials and will merge the metasurfaces with custom electronic controller nodes at the bottom of the PCB hardware platform. These electronic controllers build a nanonetwork which receives external programmatic commands and alters the metasurface structure, yielding a desired electromagnetic behavior for the Hypersurface platform.This paper will elaborate on how large scale PCB technologies are deployed for the economical manufacturing of the 4-layer Hypersurface PCB hardware platform with a size of 9"x12", having copper metasurface patches on the top of the board and the electronic controllers as 2mmx2mm WLCSP chips at 400mm pitch assembled at the bottom of the platform. The PCB platform designs have stemmed from EM modeling iterations of the whole stack of high frequency laminates taking into account also the electronic features of the controller nodes. The manufacturing processes for the realization of the selected PCB architectures will be discussed in detail.
  • Publication
    A Novel Packaging and System-Integration Platform with Integrated Antennas for Scalable, Low-Cost and High-Performance 5G mmWave Systems
    ( 2020)
    Ndip, I.
    ;
    Andersson, K.
    ;
    Kosmider, S.
    ;
    Le, T.H.
    ;
    Kanitkar, A.
    ;
    Dijk, M. van
    ;
    Senthil Murugesan, K.
    ;
    Maaß, U.
    ;
    Löher, T.
    ;
    Rossi, M.
    ;
    Jaeschke, J.
    ;
    Ostmann, A.
    ;
    Aschenbrenner, R.
    ;
    Schneider-Ramelow, M.
    ;
    Lang, K.-D.
    In this work, we present a novel packaging and system-integration platform with integrated antennas (antenna-in-package, AiP, platform) for 5G millimeter-wave (mmWave) systems. We illustrate the application of the platform for the development of miniaturized, scalable, low-cost and high-performance 5G mmWave systems for new radio (NR) base stations. RF characterization of the dielectric material of the platform and the integrated mmWave antennas as well as thermal investigations of the platform are presented. The process steps required for the fabrication of the platform are discussed, and an example of a mmWave chip embedded in the platform is shown.
  • Publication
    Embedding technologies for the manufacturing of advanced miniaturised modules toward the realisation of compact and environmentally friendly electronic devices
    ( 2019)
    Manessis, D.
    ;
    Schischke, K.
    ;
    Pawlikowski, J.
    ;
    Krivec, T.
    ;
    Schulz, G.
    ;
    Podhradsky, G.
    ;
    Aschenbrenner, R.
    ;
    Schneider-Ramelow, M.
    ;
    Ostmann, A.
    ;
    Lang, K.-D.
    The proposed work is performed in the frame of the EU project ""sustainablySMART"", which has undertaken research activities on ""Eco-innovative approaches for advanced printed circuit boards"" with the aim to demonstrate that embedding technologies are environmentally and economically beneficial since they save much surface space on main boards by embedding components in PCB layers. The main outcome is the manufacturing of robust and compact modules as sub-systems with specific functionalities. Based on this approach, the main board architecture of a voice recorder has been modified in order to be split in power, USB and DSP modules. This paper will describe the PCB embedding processes for the production of the digital signal processing (DSP) module, the power and the USB modules. In specific, for the DSP module, a 6-core layer with through vias and microvias is manufactured and then on its bottom side all the components are assembled which are going to be embedded. These components are the DSP BGA chip, voltage detector, bus buffer, etc. The components after embedding are routed to surface pads of the module. The rest of the components are assembled as SMT components on the surface of the DSP embedded module and these are the Flash memory as BGA package and 2-pad clock crystals. The DSP module (L5cm×1.5cm×2.8mm) together with the other two embedded modules will be assembled on the main board of the voice recorder. This paper will elaborate on the new design architecture of the device backbone and the assembly of all embedded modules on the backbone.
  • Publication
    Where is the Sweet Spot for Panel Level Packaging?
    ( 2019)
    Braun, T.
    ;
    Becker, K.F.
    ;
    Hölck, O.
    ;
    Voges, S.
    ;
    Wöhrmann, M.
    ;
    Böttcher, L.
    ;
    Töpper, M.
    ;
    Stobbe, L.
    ;
    Aschenbrenner, R.
    ;
    Schneider-Ramelow, M.
    ;
    Lang, K.D.
    Fan-out Wafer Level Packaging (FOWLP) is one of the latest packaging trends in microelectronics. Besides technology developments towards heterogeneous integration including multiple die packaging, passive component integration in package and redistribution layer or package-on-package approaches also larger rectangular substrates formats are targeted.
  • Publication
    Panel Level Packaging for Component Integration of an Energy Harvesting System
    ( 2019)
    Braun, T.
    ;
    Kahle, R.
    ;
    Voges, S.
    ;
    Hölck, O.
    ;
    Bauer, J.
    ;
    Becker, K.-F.
    ;
    Aschenbrenner, R.
    ;
    Dreissigacker, M.
    ;
    Schneider-Ramelow, M.
    ;
    Lang, K.-D.
    Within the European funded project smart-MEMPHIS the goal was to tackle the main challenge for all smart devices - self-powering. The project was aimed to design, manufacture and test a miniaturized autonomous energy supply based on harvesting vibrational energy with piezo-MEMS energy harvesters. Cost effective packaging was needed for 3D system integration of a MEMS-based multi-axis energy harvester, an ultra-low-power ASIC to manage the variations of the frequency and harvested power, and a miniaturized energy storing supercapacitor. Miniaturization was another key demand as target applications were a leadless pacemaker and a wireless sensor network for structural health monitoring. Panel Level Packaging (PLP) was selected as packaging technology for the harvester components. A basic study on the embedding of piezo-MEMS harvester has been performed as well as the development and proof of concept of a new PLP based supercapacitor housing. For the power management unit an ASIC together with two capacitors have been integrated by Fan-out Panel Level Packaging (FOPLP). Material selection and process development was first done on wafer level size and then transferred to large area 457×305 mm 2 panel size. Main focus was here to find a suitable material combination and process parameters for the embedding of SMD capacitors together with bare dies in a fan-out panel level package. A technology study has been performed to analyze the influence of SMD component size and pitch, thermal release tape and epoxy molding compound type during compression molding. Results have used to finally select materials for prototype built. Reliability testing have been performed to prove the overall concept and material selection for PLP.
  • Publication
    High frequency substrate technologies for the realisation of software programmable metasurfaces on PCB hardware platforms with integrated controller nodes
    ( 2019)
    Manessis, D.
    ;
    Seckel, M.
    ;
    Fu, L.
    ;
    Tsilipakos, O.
    ;
    Pitilakis, A.
    ;
    Tasolamprou, A.
    ;
    Kossifos, K.
    ;
    Varnava, G.
    ;
    Liaskos, C.
    ;
    Kafesaki, M.
    ;
    Soukoulis, C.M.
    ;
    Tretyakov, S.
    ;
    Georgiou, J.
    ;
    Ostmann, A.
    ;
    Aschenbrenner, R.
    ;
    Schneider-Ramelow, M.
    ;
    Lang, K.-D.
    The proposed work is performed in the framework of the FET-EU project "VISORSURF", which has undertaken research activities on the emerging concepts of metamaterials that can be software programmable and adapt their properties. In the realm of electromagnetism (EM), the field of metasurfaces (MSF) has reached significant breakthroughs in correlating the micro- or nano-structure of artificial planar materials to their end properties. MSFs exhibit physical properties not found in nature, such as negative or smaller-than-unity refraction index, allowing for EM cloaking of objects, reflection cancellation from a given surface and EM energy concentration in as-tight-as-possible spaces. The VISORSURF main objective is the development of a hardware platform, the Hypersurface, whose electromagnetic behavior can be defined programmatically. The key enablers for this are the metasurfaces whose electromagnetic properties depend on their internal structure. The Hypersurface hardware platform will be a 4-layer build-up of high frequency PCB substrate materials and will merge the metasurfaces with custom electronic controller nodes at the bottom of the PCB hardware platform. These electronic controllers build a nanonetwork which receives external programmatic commands and alters the metasurface structure, yielding a desired electromagnetic behavior for the Hypersurface platform. This paper will elaborate on how large scale PCB technologies are deployed for the economical manufacturing of the 4-layer Hypersurface PCB hardware platform with a size of 9" × 12", having copper metasurface patches on the top of the board and the electronic controllers as 2mm × 2mm WLCSP chips at 400 mm pitch assembled at the bottom of the platform. The PCB platform designs have stemmed from EM modeling iterations of the whole stack of high frequency laminates taking into account also the electronic features of the controller nodes. The manufacturing processes for the realization of the selected PCB architectures will be discussed in detail.
  • Publication
    Panel Level Packaging - From Idea to Industrialization -
    ( 2019)
    Braun, T.
    ;
    Becker, K.-F.
    ;
    Hoelck, O.
    ;
    Voges, S.
    ;
    Boettcher, L.
    ;
    Töpper, M.
    ;
    Stobbe, L.
    ;
    Aschenbrenner, R.
    ;
    Voitel, M.
    ;
    Schneider-Ramelow, M.
    ;
    Lang, K.-D.
    Drivers for 3D packaging solutions are manifold and each requirement calls for different answers and technologies. Main goal is miniaturization, but component density and performance, simplification of design and assembly, flexibility, functionality and finally, cost and time-to-market have been found to be the core drivers for going 3D as well. Besides die and package stacking, embedding dies is a key technology for heterogeneous system integration. There are two main approaches for embedded die technologies: Fan-out Wafer and Panel Level integration, where dies are embedded into polymer encapsulants and Chip in Polymer, where dies are embedded into the substrate.
  • Publication
    Panel Level Packaging: A View Along the Process Chain
    ( 2018)
    Braun, T.
    ;
    Becker, K.-F.
    ;
    Hölck, O.
    ;
    Kahle, R.
    ;
    Wöhrmann, M.
    ;
    Böttcher, L.
    ;
    Topper, M.
    ;
    Stobbe, L.
    ;
    Zedel, H.
    ;
    Aschenbrenner, R.
    ;
    Voges, S.
    ;
    Schneider-Ramelow, M.
    ;
    Lang, K.-D.
    Fan-out Wafer Level Packaging (FOWLP) is one of the latest packaging trends in microelectronics. Besides technology developments towards heterogeneous integration including multiple die packaging, passive component integration in package and redistribution layer or package-on-package approaches also larger substrates formats are targeted. Manufacturing is currently done on wafer level up to 12"/300 mm and 330 mm respectively. For higher productivity and therewith lower costs larger form factors are introduced. Instead of following the wafer level roadmaps to 450 mm, panel level packaging might be the next big step. Sizes considered for the panel range from 300×300 mm 2 to 457×610 mm 3 or 510×515 mm 2 up to 600×600 mm 2 or even larger influenced by different technologies coming from e.g. printed circuit board, solar or LCD manufacturing. Main challenge is here at the moment the missing standardization on panel formats. However, an easy upscaling of technology when moving from wafer to panel level is not possible. Materials, equipment and processes have to be further developed or at least adapted. A view along the process chain offers lots of possibilities but also challenges. Starting from carrier material selection for a chip first approach where not only the thermo-mechanical behavior but also properties as e.g. weight or stability should be considered. Pick and place assembly on carrier is independent from wafer or panel formats a bottleneck. Here new equipment or even new approaches for high speed but also high accuracy assembly are required. Compression molding is typically used for chip embedding and to form the reconfigured wafer or panel. Liquid, granular and sheet type molding compounds are available. All allowing chip embedding with pros and cons in cost, processability but also in cleanroom compatibility. For redistribution layer (RDL) formation a large variety of lithography tools and dielectric material options exist. As dielectrics photosensitive as well as non-photosensitive or liquid versus dry-film materials can be considered. Mask-based lithography as e.g. stepper technology is just as maskless based tools as laser direct imaging (LDI) available for panel sizes. Both offering different capabilities and strategies to overcome challenges from die placement accuracy and die shift after molding. Finally also solutions for grinding, balling and singulation are needed. Handling and especially automated handling of molded large panels including also storage and transport is still an open topic as until now only custom-made solutions exist. However, there are many process flow options also with regard to different applications. But still the question on "where is the sweet spot" taking performance, yield, cost and panel size into account is not answered yet. In summary the paper will give an overview of feasible panel level packaging processes and will provide a detailed discussion on the technology status for specific process steps and process interfaces. Finally, an outlook towards industrialization will be provided.
  • Publication
    Fan-out wafer level packaging for 5G and mm-Wave applications
    ( 2018)
    Braun, Tanja
    ;
    Becker, K.-F.
    ;
    Hoelck, O.
    ;
    Kahle, R.
    ;
    Woehrmann, M.
    ;
    Toepper, M.
    ;
    Ndip, I.
    ;
    Maass, U.
    ;
    Tschoban, C.
    ;
    Aschenbrenner, R.
    ;
    Voges, S.
    ;
    Lang, K.-D.
    Fan-out Wafer Level Packaging (FOWLP) is one of the latest packaging trends in microelectronics. FOWLP has a high potential in significant package miniaturization concerning package volume but also in thickness. Main advantages of FOWLP are the substrate-less package, lower thermal resistance, higher performance due to shorter interconnects together with direct IC connection by thin film metallization instead of wire bonds or flip chip bumps and lower parasitic effects. Especially the inductance of the FOWLP is much lower compared to FC-BGA packages. In addition the redistribution layer can also provide embedded passives (R, L, C) as well as antenna structures using a multi-layer structure. It can be used for multi-chip packages for System in Package (SiP) and heterogeneous integration. Hence, technology is well suited for RF applications.