Fraunhofer-Institut für Zuverlässigkeit und Mikrointegration IZM

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  • Publication
    Film coatings as an encapsulation process for polymer electronics
    ( 2005)
    Becker, K.-F.
    ;
    Braun, T.
    ;
    Koch, M.
    ;
    Bader, V.
    ;
    Aschenbrenner, R.
    ;
    Reichl, H.
    For improved reliability of microelectronics an encapsulation of sensitive structures is crucial, this is true especially for polymer electronics, where oxygen diffusion and water vapour ingress do dramatically influence the electrical performance. For the protection of semiconducting polymers within organic LEDs a glass layer is the method of choice, providing optimized sealing except for the edge areas. Disadvantage of glass as a sealing material is its rigidity and its sensitivity against mechanical stress. For the realization of low cost applications as smart labels / RF ID tags that need to operate within harsh environment also, besides barrier properties also mechanical protection is needed to ensure device functionality. Various approaches are taken to apply such barrier layers, typically CVD/PVD or spin coating are used, to yield thin, homogeneous layers of encapsulants of 1 to 5 µm thickness. For the high speed encapsulation of large areas also lamination is discussed, where multilayer films are applied using temperature and pressure, layer thickness is in the range of 5 to 30 µm. As a further technology, suited for the deposition of low viscosity liquid barrier materials, film coating processes are proposed. Focus of the technology development described is the application of homogeneous coating on large areas. Expected advantage is the contactless application at high speed on large area substrates, especially useful on substrates showing a 3D topography, as present with devices integrating heterogeneous structures as OSC, printed passives or coils. At Fraunhofer IZM film coating equipment has been installed and first evaluations show promising results. With an ORMOCER® material supplied by Fraunhofer ISC a coating of PET films was demonstrated resulting in a homogeneous coating with a minimum thickness below 10 µm.
  • Publication
    Film coating - large area encapsulation process for electronics packaging
    ( 2005)
    Becker, K.-F.
    ;
    Braun, T.
    ;
    Koch, M.
    ;
    Bader, V.
    ;
    Aschenbrenner, R.
    ;
    Reichl, H.
    For improved reliability of microelectronics an encapsulation of sensitive structures is crucial, this is true especially for polymer electronics, where oxygen diffusion and water vapor ingress do dramatically influence the electrical performance. For the protection of semiconducting polymers within organic LEDs a glass layer is the method of choice, providing optimized sealing except for the edge areas. Disadvantage of glass as a sealing material is its rigidity and its sensitivity against mechanical stress. For the realization of low cost applications as smart labels / RF ID tags besides barrier properties also mechanical protection is needed to ensure device functionality. This is especially true when these devices need to operate within harsh environment. Various approaches are possible to apply such barrier layers, typically CVD/PVD or spin coating are used, to yield thin, homogeneous layers of encapsulants of 1 to 5 µm thickness. For the high speed encapsulation of large areas also lamination is discussed, where multilayer films are applied using temperature and pressure, layer thickness is in the range of 5 to 30 µm. As a further technology, suited for the deposition of low viscosity liquid barrier materials, film coating processes are proposed. Focus of the technology development described is the application of homogeneous coating on large areas. Expected advantage is the contactless application at high speed on large area substrates, especially useful on substrates showing a 3D topography, as present with devices integrating heterogeneous structures as organic semiconductors (OSC), printed passives or coils. At Fraunhofer IZM film coating equipment has been installed and first evaluations of show promising results in large area coating on flexible substrates.
  • Publication
    Chip in duromer technology for system in package realization
    ( 2005)
    Becker, K.-F.
    ;
    Braun, T.
    ;
    Neumann, A.
    ;
    Ostmann, A.
    ;
    Koch, M.
    ;
    Bader, V.
    ;
    Aschenbrenner, R.
    ;
    Reichl, H.
    The Chip in Duromer technology for realization of stackable SIPs, is similar to conventional Molded Interconnect Device (MID) technology, that is usually realized using thermoplastic polymers, combining the functionality of housing and substrate into one device. Advantages of the conventional MID technology are the reduction of parts during assembly by integrating mechanical and electrical functionality into a device and the reduction of space, as MID allows a 3D integration of devices. Disadvantage of conventional technology, especially if combined with typical technical thermoplastics is the large mismatch in coefficient of thermal expansion (CTE) between substrate and advanced microelectronic components as CSP or flip chip. This is reducing the applicability of thermoplastic MID to moderate temperature ranges and/or to rather robust components. To overcome this disadvantage the use of low CTE Duromer as Epoxy Molding Compounds (EMC) as base material for device assembly is proposed, generating a unique technology well adapted to SIP and MEMS packaging needs, the Duromer MID approach. The technological realization of Chip in Duromer uses equipment involved are conventional backend processes as IC bonding to Flex, transfer molding using epoxy molding compounds, laser machining, metallization and structurization processes well known from PCB processing. The use of existing equipment allows both, a rather fast process implementation and a cost effective manufacturing of the components. Within this paper a description of a generic packaging technology integrating detailed analysis of metallization processes and assembly issues. Summarized this paper presents further process development and feasibility analysis of wafer level packaging technologies for SiP solutions based on a Chip in Duromer approach.
  • Publication
    Duromer MID technology for system-in-package generation
    ( 2005)
    Becker, K.-F.
    ;
    Braun, T.
    ;
    Neumann, A.
    ;
    Ostmann, A.
    ;
    Koch, M.
    ;
    Bader, V.
    ;
    Aschenbrenner, R.
    ;
    Reichl, H.
    ;
    Jung, E.
    The Duromer MID technology for realization of stackable SIPs is similar to conventional Molded Interconnect Device (MID) technology, which is usually realized using thermoplastic polymers, combining the functionality of housing and substrate into one device. Advantages of the conventional MID technology are the reduction of parts during assembly by integrating mechanical and electrical functionality into a device and the reduction of space, as MID allows a 3D integration of devices. Disadvantage of conventional technology, especially if combined with typical technical thermoplastics is the large mismatch in coefficient of thermal expansion (CTE) between substrate and advanced microelectronic components as CSP or flip chip. This is reducing the applicability of thermoplastic MID to moderate temperature ranges and/or to rather robust components. To overcome this disadvantage the use of low CTE duromer as Epoxy Molding Compounds (EMC) as base material for device assembly is proposed, generating a unique technology well adapted to SIP and MEMS packaging needs, the Duromer MID approach. The technological realization of Duromer MID uses conventional backend processes as IC bonding to flex, transfer molding using epoxy molding compounds, laser machining, metallization and structurization processes well known from PCB processing. The use of existing equipment allows both, a rather fast process implementation and a cost effective manufacturing of the components. Within this paper the investigations described previously [1] are driven further towards a description of a generic packaging technology integrating detailed analysis of metallization processes and assembly issues. Summarized this paper presents further process development and feasibility analysis of wafer level packaging technologies for SiP solutions based on a Duromer MID approach.
  • Publication
    Flip chip molding - highly reliable flip chip encapsulation
    ( 2002)
    Braun, T.
    ;
    Becker, K.F.
    ;
    Koch, M.
    ;
    Bader, V.
    ;
    Aschenbrenner, R.
    ;
    Reichl, H.
    Flip chip technology has the shortest interconnect length for minimum signal disturbance and simultaneous interconnection leading to reduced process times especially for high I/O counts and for RF applications. Flip chip technology allows for reliabilities required for automotive applications, but to achieve this goal, a plastic encapsulant, the so called underfiller, has to be used. New material developments for transfer molding allow underfilling and overmolding in one single transfer molding step. Existing standard equipment for encapsulation can be used and no additional process step for underfill dispensing is required. Molded flip chips have the potential of high reliability as the low CTE of the flip chip molding compound reduces the thermal mismatch. State of the art in FC molding is the encapsulation of single chip packages as BGA or CSP. Trends of the market drive towards SIPs with an integration of different devices as e.g. SMD and FC. Therefore the highly reliable encapsulation of these hybrid packages with inhomogeneous topography is the future goal. For the qualification of flip chip molding a test vehicle has been designed at Fraunhofer IZM. This test vehicle for process evaluation allows the encapsulation and underfilling of a single flip chip.
  • Publication
    Alternative solders for flip chip applications in the automotive environment
    ( 1998)
    Jung, E.
    ;
    Heinricht, K.
    ;
    Klöser, J.
    ;
    Aschenbrenner, R.
    ;
    Reichl, H.
    In addition to Pb toxicity, there are other problems with SnPb solders. In automotive applications, where solder joints are subjected to thermal cycles, severe vibrations, sustained temperatures up to 150 degrees C and peak temperatures of 180 degrees C, the critical failure mode of eutectic SnPb solder in assemblies is bump fatigue. For flip chip technology, induced thermal stresses and strains in solder joints are very hazardous. This paper presents a flip chip process based on electroless Ni/Au bumping and stencil printing of solder paste on wafers. Chemical nickel plating combined with solder printing is a very flexible and cost effective bumping method. The basic process steps and key aspects of this technology are described in detail. Experimental results for an ultra fine pitch printing technique on wafers are shown, and reflowed solder bumps are characterized for uniformity and strength. In comparison to eutectic SnPb, SnBiCu, SnAg, SnCu, and AuSn solder alloys are selected and investigated. The alloys are compared for flip chip technology applicability, microstructure and phase compositions are presented. Microstructure coarsening and phase growth after thermal aging are also investigated. In order to investigate substrate material CTE effects on reliability, flip chip assembly was performed on low temperature cofired ceramic (LTCC) and FR-4 substrates. The flip chip joint quality was investigated by metallurgical cross sections and electrical and mechanical measurements. Finally, the reliability results of these joints after thermal cycling with and without underfill on both types of substrate materials are presented.
  • Publication
    Reliability aspects of molded BGA's related to material properties
    ( 1998)
    Ehrlich, R.
    ;
    Becker, K.-F.
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    Badri Ghavifekr, H.
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    Ansorge, F.
    ;
    Aschenbrenner, R.
    ;
    Reichl, H.
    ;
    Sawai, K.
    ;
    Tanaka, A.
    ;
    Kumano, K.
    ;
    Tenya, Y.
    ;
    Chichon, M.
    ;
    Hosokawa, H.
    BGA packages have become increasingly popular for microprocessor device packaging and MCM assembly. This is due to the advantages the ball grid array offers with regard to high lead count combined with large pitches, processable with standard SMT equipment. For BGA package encapsulation, epoxy resins are mostly used, either as glob top or molding compound. For cost effective encapsulation of large numbers of BGA packages, the transfer mold process offers various advantages. The process is fully automated with short process times and the molding compound glass transition temperature (Tg) is very high (>200 degrees C) compared to glob top encapsulants ( 160 degrees C) offering higher reliability at elevated temperatures. However, BGA packages challenge both material suppliers and packagers as this package type is asymmetric and is thus very sensitive to encapsulant material properties. Properties to consider are reduced encapsulation material shrinkage after molding to provide low warpage, and optimized molding compound adhesion to the materials present in a BGA to avoid delaminations that might cause electrical failures. Fraunhofer IZM and Toshiba Chemical have designed test vehicles to investigate different BGA molding compounds with regard to substrate adhesion with various types of solder resist after molding and after package reliability testing. Results of these investigations are reported and investigations regarding humidity sensitivity (according to JEDEC Std. 020) of the encapsulated BGA and the relationship between adhesive strength of EMC to solder mask and humidity uptake of the package are described.
  • Publication
    Implementation of flip chip technology into volume manufacturing demonstration of processes
    ( 1998)
    Jung, E.
    ;
    Heinricht, K.
    ;
    Kutzner, K.
    ;
    Klöser, J.
    ;
    Aschenbrenner, R.
    ;
    Reichl, H.
    ;
    Brommelhaus, A.
    Until now, use of flip chip technology has not been widespread in volume manufacturing, although it provides a number of significant advantages over standard surface mount devices. In particular, the cost aspect of using flip chip technology in a large scale manufacturing environment is expected to overcome the remaining issues. In order to illustrate the equipment and processes involved for incorporation of flip chip attachment into a production process, a demonstration center was established at FhG-IZM. Critical process steps were identified and addressed. This article gives a detailed insight into the actual implementation of a flip chip process into a SMD compatible production line, highlighting aspects of bump provision, cleaning, chip placement and underfilling. Bumping covers low cost processes such as electroless nickel as under-bump metallization (UBM) and stencil printed solder deposits using advanced printing technology. The necessity of cleaning and the key aspects for achievement of high reliability with industrial applied processes is highlighted. Required features of the placement machine and related critical issues are presented. Underfill application is also covered, focussing on important aspects for process optimization.
  • Publication
    Adhesive flip chip bonding on flexible substrates
    ( 1997)
    Aschenbrenner, R.
    ;
    Mießner, R.
    ;
    Reichl, H.
    Flip chip attachments provide the highest interconnect density possible, making this technology attractive for use with flexible high density substrates. This paper presents three flip chip adhesive process methods based on flexible polyimide and polyester substrates using gold, nickel/gold and gold stud bumps. Isotropic conductive adhesives are promising for adhesive joining, as they conduct electricity equally in all directions. To use such adhesives in flip chip applications, the material must be applied precisely to the points to be connected, and must be not allowed to flow and short circuit between circuit lines. Anisotropically conductive adhesive materials are prepared by dispersing conductive particles in an adhesive matrix at a concentration high enough to assure reliable conductivity between substrate and IC electrodes. Another possibility is the use of nonconductive adhesives and Au-bumped chips, which are bonded via thermocompression to the substrate. During bonding, the bumps pierce a nonconducting adhesive foil and make the electrical contact while the adhesive supplies mechanical stability. Moreover, the adhesive fills the gap between chip and substrate, relieving the bumps of mechanical stress due to the different CTEs. Reliability evaluation was performed with specific regard to the interface reactions between polymers and metal surfaces in adhesive contacts. The electrical and mechanical performance of the adhesive bonds were studied by evaluating initial contact resistance as a function of temperature and humidity.
  • Publication
    Fluxless flip chip bonding on flexible substrates
    ( 1996)
    Zakel, E.
    ;
    Aschenbrenner, R.
    ;
    Azdasht, G.
    ;
    Klöser, J.
    ;
    Reichl, H.
    During the last few years an increasing number of flip chip (FC) interconnection technologies have emerged. While flip chip assembly offers many advantages compared to conventional packaging techniques, several aspects hinder this technology from entering the high volume market. Among these are the availability of bumped chips and the costs for the substrates, i.e. ceramic substrates with closely matching coefficient of thermal expansion (CTE) to the chip, in order to maintain a high reliability. Only recently, with the possibility of filling the gap between chip and organic substrate with an encapsulant, was the reliability of flip chips mounted on organic substrates significantly enhanced. This paper presents two approaches to a fluxless process, the one based on soldering techniques using the Au-Sn metallurgy and the other on adhesive joining techniques. Soldering is performed with a thermode and with a laser based system. For both of these FC-joining processes, alternative bump metallurgies based on electroplated gold, electroplated gold-tin, mechanical gold and electroless nickel gold bumps are applied.