Fraunhofer-Institut für Zuverlässigkeit und Mikrointegration IZM

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  • Publication
    Fan-Out Wafer and Panel Level Packaging - A Platform for 3D Integration
    ( 2021)
    Braun, T.
    ;
    Becker, K.-F.
    ;
    Töpper, M.
    ;
    Aschenbrenner, R.
    ;
    Schneider-Ramelow, M.
    The constant drive to further miniaturization and heterogeneous system integration leads to a need for new packaging technologies that also allow large area processing and 3D integration with strong potential for low cost applications. Here, Fan-Out Wafer Level Packaging [FOWLP] is one of the latest packaging trends in microelectronics. The technology can be also used for multi-chip packages or System in Package (SiP). 3D integration is typically done by package on package (PoP) stacking where the electrical 3D routing is done by through mold (TMV) or through package vias (TPV) and a redistribution layer on both sides of the FOWLP. In summary the paper will give a review of the different technology approaches for through mold vias in a Fan-out Wafer or Panel Level Package.
  • Publication
    Panel Level Packaging - From Idea to Industrialization -
    ( 2019)
    Braun, T.
    ;
    Becker, K.-F.
    ;
    Hoelck, O.
    ;
    Voges, S.
    ;
    Boettcher, L.
    ;
    Töpper, M.
    ;
    Stobbe, L.
    ;
    Aschenbrenner, R.
    ;
    Voitel, M.
    ;
    Schneider-Ramelow, M.
    ;
    Lang, K.-D.
    Drivers for 3D packaging solutions are manifold and each requirement calls for different answers and technologies. Main goal is miniaturization, but component density and performance, simplification of design and assembly, flexibility, functionality and finally, cost and time-to-market have been found to be the core drivers for going 3D as well. Besides die and package stacking, embedding dies is a key technology for heterogeneous system integration. There are two main approaches for embedded die technologies: Fan-out Wafer and Panel Level integration, where dies are embedded into polymer encapsulants and Chip in Polymer, where dies are embedded into the substrate.
  • Publication
    Panel Level Packaging for Component Integration of an Energy Harvesting System
    ( 2019)
    Braun, T.
    ;
    Kahle, R.
    ;
    Voges, S.
    ;
    Hölck, O.
    ;
    Bauer, J.
    ;
    Becker, K.-F.
    ;
    Aschenbrenner, R.
    ;
    Dreissigacker, M.
    ;
    Schneider-Ramelow, M.
    ;
    Lang, K.-D.
    Within the European funded project smart-MEMPHIS the goal was to tackle the main challenge for all smart devices - self-powering. The project was aimed to design, manufacture and test a miniaturized autonomous energy supply based on harvesting vibrational energy with piezo-MEMS energy harvesters. Cost effective packaging was needed for 3D system integration of a MEMS-based multi-axis energy harvester, an ultra-low-power ASIC to manage the variations of the frequency and harvested power, and a miniaturized energy storing supercapacitor. Miniaturization was another key demand as target applications were a leadless pacemaker and a wireless sensor network for structural health monitoring. Panel Level Packaging (PLP) was selected as packaging technology for the harvester components. A basic study on the embedding of piezo-MEMS harvester has been performed as well as the development and proof of concept of a new PLP based supercapacitor housing. For the power management unit an ASIC together with two capacitors have been integrated by Fan-out Panel Level Packaging (FOPLP). Material selection and process development was first done on wafer level size and then transferred to large area 457×305 mm 2 panel size. Main focus was here to find a suitable material combination and process parameters for the embedding of SMD capacitors together with bare dies in a fan-out panel level package. A technology study has been performed to analyze the influence of SMD component size and pitch, thermal release tape and epoxy molding compound type during compression molding. Results have used to finally select materials for prototype built. Reliability testing have been performed to prove the overall concept and material selection for PLP.
  • Publication
    Panel Level Packaging: A View Along the Process Chain
    ( 2018)
    Braun, T.
    ;
    Becker, K.-F.
    ;
    Hölck, O.
    ;
    Kahle, R.
    ;
    Wöhrmann, M.
    ;
    Böttcher, L.
    ;
    Topper, M.
    ;
    Stobbe, L.
    ;
    Zedel, H.
    ;
    Aschenbrenner, R.
    ;
    Voges, S.
    ;
    Schneider-Ramelow, M.
    ;
    Lang, K.-D.
    Fan-out Wafer Level Packaging (FOWLP) is one of the latest packaging trends in microelectronics. Besides technology developments towards heterogeneous integration including multiple die packaging, passive component integration in package and redistribution layer or package-on-package approaches also larger substrates formats are targeted. Manufacturing is currently done on wafer level up to 12"/300 mm and 330 mm respectively. For higher productivity and therewith lower costs larger form factors are introduced. Instead of following the wafer level roadmaps to 450 mm, panel level packaging might be the next big step. Sizes considered for the panel range from 300×300 mm 2 to 457×610 mm 3 or 510×515 mm 2 up to 600×600 mm 2 or even larger influenced by different technologies coming from e.g. printed circuit board, solar or LCD manufacturing. Main challenge is here at the moment the missing standardization on panel formats. However, an easy upscaling of technology when moving from wafer to panel level is not possible. Materials, equipment and processes have to be further developed or at least adapted. A view along the process chain offers lots of possibilities but also challenges. Starting from carrier material selection for a chip first approach where not only the thermo-mechanical behavior but also properties as e.g. weight or stability should be considered. Pick and place assembly on carrier is independent from wafer or panel formats a bottleneck. Here new equipment or even new approaches for high speed but also high accuracy assembly are required. Compression molding is typically used for chip embedding and to form the reconfigured wafer or panel. Liquid, granular and sheet type molding compounds are available. All allowing chip embedding with pros and cons in cost, processability but also in cleanroom compatibility. For redistribution layer (RDL) formation a large variety of lithography tools and dielectric material options exist. As dielectrics photosensitive as well as non-photosensitive or liquid versus dry-film materials can be considered. Mask-based lithography as e.g. stepper technology is just as maskless based tools as laser direct imaging (LDI) available for panel sizes. Both offering different capabilities and strategies to overcome challenges from die placement accuracy and die shift after molding. Finally also solutions for grinding, balling and singulation are needed. Handling and especially automated handling of molded large panels including also storage and transport is still an open topic as until now only custom-made solutions exist. However, there are many process flow options also with regard to different applications. But still the question on "where is the sweet spot" taking performance, yield, cost and panel size into account is not answered yet. In summary the paper will give an overview of feasible panel level packaging processes and will provide a detailed discussion on the technology status for specific process steps and process interfaces. Finally, an outlook towards industrialization will be provided.
  • Publication
    Fan-out wafer level packaging for 5G and mm-Wave applications
    ( 2018)
    Braun, Tanja
    ;
    Becker, K.-F.
    ;
    Hoelck, O.
    ;
    Kahle, R.
    ;
    Woehrmann, M.
    ;
    Toepper, M.
    ;
    Ndip, I.
    ;
    Maass, U.
    ;
    Tschoban, C.
    ;
    Aschenbrenner, R.
    ;
    Voges, S.
    ;
    Lang, K.-D.
    Fan-out Wafer Level Packaging (FOWLP) is one of the latest packaging trends in microelectronics. FOWLP has a high potential in significant package miniaturization concerning package volume but also in thickness. Main advantages of FOWLP are the substrate-less package, lower thermal resistance, higher performance due to shorter interconnects together with direct IC connection by thin film metallization instead of wire bonds or flip chip bumps and lower parasitic effects. Especially the inductance of the FOWLP is much lower compared to FC-BGA packages. In addition the redistribution layer can also provide embedded passives (R, L, C) as well as antenna structures using a multi-layer structure. It can be used for multi-chip packages for System in Package (SiP) and heterogeneous integration. Hence, technology is well suited for RF applications.
  • Publication
    Recent developments in panel level packaging
    ( 2018)
    Braun, T.
    ;
    Billaud, M.
    ;
    Zedel, H.
    ;
    Stobbe, L.
    ;
    Becker, K.-F.
    ;
    Hoelck, O.
    ;
    Wöhrmann, M.
    ;
    Boettcher, L.
    ;
    Töpper, M.
    ;
    Aschenbrenner, R.
    ;
    Voges, S.
    ;
    Lang, K.-D.
    ;
    Schneider-Ramelow, M.
    Panel Level packaging (PLP) is one of the latest packaging trends in microelectronics. Besides technology developments towards heterogeneous integration also larger substrates formats are targeted. Fan-out Wafer Level manufacturing is currently done on wafer level up to 12""/300 mm and 330 mm diameter respectively. For higher productivity and therewith lower costs, larger form factors are introduced. Instead of following the wafer level roadmaps to 450 mm, panel level packaging might be the next big step. Upscaling of technology when moving from wafer to panel level as well as the use or adaptation of existing large area tools and materials as e.g. from Printed Circuit Board (PCB) or Liquid Crystal Display (LCD) manufacturing is not possible. Additionally, the missing standardization in sizes is another challenge. Considered panel dimensions ranges from 300x300 mm 2 to 457x610 mm 3 or 510x515 mm 2 up to 600x600 mm 2 or even larger. The paper will describe recent developments along the process chain including materials for carrier selection, encapsulation and redistribution layer as well as the related process and equipment options. Especially the redistribution layer (RDL) application offers a variety of technology options. In addition, main challenges as warpage, die shift and panel handling in PLP will be discussed. However, for industrialization also the understanding of the cost structure and cost opportunities are important - also referring to the different technology options. Therefore, a highly granular cost model is introduced and application scenarios are presented.
  • Publication
    Potential and challenges of fan-out panel level packaging
    ( 2016)
    Braun, T.
    ;
    Becker, K.-F.
    ;
    Kahle, R.
    ;
    Raatz, S.
    ;
    Töpper, M.
    ;
    Aschenbrenner, R.
    ;
    Voges, S.
    ;
    Wöhrmann, M.
    ;
    Lang, K.-D.
    Fan-out Wafer Level Packaging (FOWLP) is one of the latest packaging trends in microelectronics. The technology has a high potential in significant package miniaturization concerning package volume but also in thickness. Manufacturing is currently done on wafer level up to 12"/300 mm and 330 mm respectively. For higher productivity and therewith lower costs larger form factors are forecasted for the near future. Instead of following the wafer level approach to 450 mm, panel level packaging will be the next big step. Sizes for the panel could range up to 18"×24" or even larger influenced by different technologies coming from e.g. printed circuit board, solar or LCD manufacturing. However, an easy upscaling of technology when moving from wafer to panel level is not possible. Materials, equipment and processes have to be further developed or at least adapted. An overview of state of technology for panel level packaging will be presented and discussed in detailed.
  • Publication
    Precision jetting of solder paste - a versatile tool for small volume production
    ( 2014)
    Becker, K.-F.
    ;
    Koch, M.
    ;
    Voges, S.
    ;
    Thomas, T.
    ;
    Fliess, M.
    ;
    Bauer, J.
    ;
    Braun, T.
    ;
    Aschenbrenner, R.
    ;
    Schneider-Ramelow, M.
    ;
    Lang, K.-D.
    During the last years, jetting processes for higher viscosity materials have gained widespread interest in microelectronics manufacturing. Main reasons for this interest are high throughput/productivity of jetting, contactless material deposition, high volume precision and freely designable deposition patterns. In previous studies [i,ii] we have demonstrated the jet ability of different resin-based materials, being exemplary for unfilled adhesive, for low viscous Underfill resin and for higher viscosity Glob Top materials. The focus of our previous work was on the dosing of various encapsulants - Underfill material with low viscosity and near Newtonian behaviour and Glob Top resins, being non-Newtonian fluids due to higher matrix viscosity and higher filler content (up to 70 wt %) with resulting increased filer/filler and filler/matrix interaction. During the last years jetting has become widely used and has been applied to the dosing of much more complex materials, combining high viscosity matrix materials with odd shaped and compressive particles. Examples for these materials are conductive adhesives and also solder pastes, where the jetting system developed by Swedish company My data set's the current standard for solder paste jetting. In a technological study solder paste jetting using different jetting systems has been investigated in comparison to solder paste dispensing and solder paste printing, especially material rheological behaviour and the correspondence to process ability have been evaluated in detail. To illustrate the potential of solder paste jetting as a flexible and powerful tool for electronic system prototyping, a test vehicle has been designed, containing areas for SMD soldering and for process reproducibility. To determine process quality not only basic process data on droplet diameter, resulting material depot size and positioning accuracy have been evaluated, but also statistical means have been employed to determine process homogeneity and stability depending on the respective parameter set. Summarized this paper gives an insight into solder jet process development and describes material rheology demands and limitations and thus allows the optimized use of advanced solder jetting technology for electronics assemblies.
  • Publication
    Panel level packaging for LED lighting
    ( 2013)
    Braun, T.
    ;
    Bauer, J.
    ;
    Becker, K.-F.
    ;
    Kahle, R.
    ;
    Bader, V.
    ;
    Voges, S.
    ;
    Jordan, R.
    ;
    Aschenbrenner, R.
    ;
    Lang, K.D.
    General lighting by use of LED-Chips is one of the strongly growing markets today and also in future. One of the trends goes to LEDs with higher and higher luminous fluxes per chip area to get the best price per lumen on the market. Unfortunately, such large LEDs produce a lot of heat, which must be spread to avoid overheating and shorter lifetime of the LEDs. Another approach is the use of many small LEDs so that both light and heat source are spread into a larger area. Cost-effective established PCB-technology was applied to produce large-area light sources consisting of many small LED chips placed and electrically connected on a PCB-substrate. LEDs were ICA-bonded with their bottom pad to the PCB. The top contacts of the LEDs were established by laminating an adhesive copper sheet followed by a LDI structuring as known from PCB-via-technology. This assembly can then be completed by adding converting and light forming optical elements.
  • Publication
    From wafer level to panel level mold embedding
    ( 2013)
    Braun, Tanja
    ;
    Becker, K.-F.
    ;
    Voges, S.
    ;
    Thomas, T.
    ;
    Kahle, R.
    ;
    Bauer, J.
    ;
    Aschenbrenner, R.
    ;
    Lang, K.-D.
    The constant drive to further miniaturization and heterogeneous system integration leads to a need for new packaging technologies which also allow large area processing and 3D integration with potential for low cost applications. Large area mold embedding technologies and embedding of active components into printed circuit boards (Chip-inPolymer) are two major packaging trends in this area. Mold embedding is currently done on wafer level, typically with diameters of 8" to 12", for future process optimization, PCB technologies offer the potential of real large areas up to 610 × 457 mm2. For mold embedding as e.g. for fan-out wafer level packaging compression molding equipment is used in combination with liquid, granular or sheet epoxy molding compounds, with the boundary condition, that mold processes do need a product specific tool (with defined diameter & thickness). Within this paper the potential of tool-less lamination processes, a standard in PCB manufacturing, is evaluated. Lamination is done in panel format using well-known molding compounds from wafer level compression molding. To evaluate the potential of today's encapsulants for large area embedding processes, different liquid, granular and sheet molding compounds have been intensively evaluated on their processability, on process & material induced die shift and on resulting warpage - all on panel level. Acting as an interconnection layer, PCB based redistribution technologies using lamination of resin coated copper (RCC) films are used. Within the paper, different RCC materials are introduced and discussed concerning their reliability potential based on the available layer thicknesses and thermo-mechanical material properties. The feasibility of the proposed technologies is demonstrated using a two chip package. Dies are embedded in panel size by lamination technologies. Subsequently the wiring is done by lamination of an RCC film over the embedded cmponents and on the panel backside for double sided redistribution. In a process flow also similar to conventional PCB manufacturing µvias to the die pads and through mold vias are drilled using a UV laser and are metalized by Cu-electroplating in one step. This way dies are connected to the front copper layer as well as front to backside of the panel. Conductor lines and pads are formed by Cu etching. Finally, a solder mask and a solderable surface finish are applied. If solder depots are necessary, e.g. for BGA packages, those can be applied by solder balling equipment - either by printing or by preform attach. In summary this paper describes the potential to move from wafer level to panel level mold embedding technology in combination with PCB based redistribution processes. The technology described offers a cost effective packaging solution for e.g. single chip packages as well as for future sensor/ASIC systems or processor/memory stacks in volume production.