Fraunhofer-Institut für Zuverlässigkeit und Mikrointegration IZM

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  • Patent
    Verfahren zum Bilden einer strukturierten Metallisierung auf einem Halbleiterwafer
    ( 2002)
    Aschenbrenner, R.
    ;
    Azdasht, G.
    ;
    Zakel, E.
    ;
    Ostmann, A.
    ;
    Motulla, G.
    A process for forming a structured metallisation on a semiconductor wafer (20), in which a passivation layer (22) is applied onto the wafer main surface and is structured to define a bond pad (24), involves (a) producing a metal bump on the bond pad (24); (b) producing an activated dielectric on the passivation layer regions on which the structured metallisation is to be formed; and (c) chemically depositing metal on the activated dielectric and the metal bump. Also claimed are alternative processes involving (i) carrying out step (b), activating the bond pad and chemically depositing metal on the activated regions and the activated bond pad; (ii) producing an activated electrically conductive paste (40) on the bond pad (24) and on the passivation layer regions on which the structured metallisation is to be formed, followed by chemical metal deposition on the paste (40); or (iii) carrying out step (a), producing a structured metal foil on the metal bump and on the passivation layer reg ions on which the structured metallisation is to be formed, followed by chemical metal deposition on the metal foil. USE - Especially for chip wiring production on a semiconductor wafer. ADVANTAGE - Wiring of chip edge pads of the wafer in a planar configuration can be carried out in a simpler, quicker and less expensive manner than conventional processes which employ expensive sputtering operations.