Fraunhofer-Institut für Angewandte und Integrierte Sicherheit AISEC

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  • Publication
    Smart Intersections Improve Traffic Flow and Safety
    ( 2019)
    Striegel, Martin
    ;
    Otto, Thomas
    Smart intersections help to address increasing traffic density and improve road safety. By leveraging data from infrastructure sensors, and combining and supplying those data to road users, their perception can be improved. This aids in protecting vulnerable road users (VRUs) and acts as a crucial building block for enabling automated and autonomous driving.
  • Publication
    Low-latency X25519 hardware implementation
    ( 2017)
    Koppermann, P.
    ;
    Santis, F. de
    ;
    Heyszl, J.
    ;
    Sigl, G.
    In the past few years, there has been a growing interest in Curve25519 due to its elegant design aimed at both high-security and high-performance, making it one of the most promising candidates to secure IoT applications. Until now Curve25519 hardware implementations were mainly optimized for high throughput applications, while no special care was given to low-latency designs. In this work, we close this gap and provide a Curve25519 hardware design targeting low-latency applications. We present a fast constant-time variable-base-point elliptic curve scalar multiplication using Curve25519 that computes a session key in less than 100 its. This is achieved by using a high-speed prime field multiplier that smartly combines the reduction procedure with the summation of the digit-products. As a result, our presented implementation requires only 10465 cycles for one session key computation. Synthesized on a Zynq-7030 and operating with a clock frequency of 115 MHz this translates to a latency of 92 kts which represents an improvement of factor 3.2 compared to other Curve25519 implementations. Our implementation uses Montgomery ladder as the scalar multiplication algorithm and includes randomized projective coordinates to thwart side-channel attacks.
  • Publication
    Efficient security zones implementation through hierarchical group key management at NoC-based MPSoCs
    ( 2017)
    Sepulveda, J.
    ;
    Flórez, D.
    ;
    Immler, V.
    ;
    Gogniat, G.
    ;
    Sigl, G.
    Sensitive applications are split into the IP cores of the Multi-Processors System-on-Chip (MPSoCs). In order to isolate the sensitive communication among such IP cores, security zones based on conference keys agreement can be built. However, the flexibility and dynamic nature of MPSoCs force reshaping the security zones at runtime. It is still a challenge to achieve efficient computation and distribution of new conference keys in MPSoC environments. In order to solve this problem, in this work we propose the combination of two techniques: i) high performance NoC, able to efficiently communicate data and control packets in the system; and ii) hierarchical group-key management for efficient security zone modification. We implement three hierarchical protocols and we show that by decentralizing the security management of the rekeying process and using a two-level NoC, it is possible to achieve an improvement of the performance compared to the previous flat approaches.
  • Publication
    Fast and reliable PUF response evaluation from unsettled bistable rings
    ( 2017)
    Hesselbarth, R.
    ;
    Heyszl, J.
    ;
    Sigl, G.
    Bistable ring (BR) based strong PUFs are promising candidates for lightweight authentication applications. It has been observed that a good '0'/'1'-balance of their responses correlates with longer settling times. This is problematic, since the state-of-the-art evaluation method requires the BR to be settled in order to generate a reliable PUF response. We show that settling times can easily extend beyond 100 ms for 70 percent of the responses in the TBR PUF, which is a BR-based PUF with good '0'/'1'-balance characteristics. Hence, it is practically impossible to wait for all BRs to settle, which results in a reliability penalty. In order to solve this problem, we present three new methods, which allow the evaluation of unsettled BRs with increased reliability compared to the state-of-the-art method. We were able to improve response reliability from 81 percent to up to 98.5 percent and achieve response reliabilities of 97 percent at an evaluation time of 320 ns. This enables the fast and reliable use of BR-based PUFs in strong PUF applications.
  • Publication
    Closing the gap between speed and configurability of multi-bit fault emulation environments for security and safety-critical designs
    ( 2015)
    Nyberg, R.
    ;
    Heyszl, J.
    ;
    Rabe, D.
    ;
    Sigl, G.
    Steadily decreasing transistor sizes and new multi beam laser attacks lead to an increasing amount of multi-bit fault occurrences, e.g., during fault attacks against cryptographic implementations. Therefore, multi-bit fault injection becomes more important during security and safety verification. Fault injection techniques which are applicable during the development cycle of a device are based on either software implementations, e.g. formal methods and simulations, or fault emulation environments in hardware. So far, simulations provide the best configurability whereas fault emulation environments provide the best performance in terms of run time. This contribution presents an FPGA-based emulation environment that combines the advantages of both simulation-based and emulation-based environments. To the best of our knowledge, we are the first to achieve this. Permanent and transient multi-bit faults are configurable at run time where the selection of a fault model, the configuration of the injection time and fault duration is supported without the need for re-synthesizing the design. We propose three measures for performance optimization allowing us to support all the fault configuration capabilities at run time without performance penalty. Experimental results are provided for a hardened 8051-like microprocessor showing that the presented emulation environment reaches the theoretical optimal performance for a wide range of fault configurations using our proposed optimizations.