A computing unit, method to perform computations, method to generate program code for a hardware comprising a multi-stage-buffer and program code

Krüger, JensJensKrügerFütterling, ValentinValentinFütterlingBednara, MarcusMarcusBednaraSchuhmann, NorbertNorbertSchuhmann2024-04-252024-04-252022-01-12https://publica.fraunhofer.de/handle/publica/466943A computing unit (100), comprises first circuitry (110) configured to determine at least one memory address based on a first program code and to receive data stored at the memory address. A second circuitry (120) is configured to perform arithmetic operations based on a second program code using the received data.enA computing unit, method to perform computations, method to generate program code for a hardware comprising a multi-stage-buffer and program codeRecheneinheit, Verfahren zum Durchführen von Berechnungen, Verfahren zum Erzeugen von Programmcode für eine Hardware mit einem mehrstufigen Puffer und ProgrammcodepatentEP3937009 A1EP20200185002