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  4. Layout-aware Analog Design Optimization using Intelligent IP Generators
 
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May 6, 2026
Poster
Title

Layout-aware Analog Design Optimization using Intelligent IP Generators

Title Supplement
Poster presented at the edaWorkshop26, 5. bis 6. Mai 2026 in Dresden
Abstract
Motivation of the work:
- Complex dependencies among design and layout parameters complicate finding optimal solutions
- Layout effects are often dominated by parasitic elements
Our Approach:
- Initial sampling of design space including layout
- Determine parasitic elements and other layout properties
- Determine most sensitive parameters
- Optimize
Author(s)
Reich, Torsten  orcid-logo
Fraunhofer-Institut für Integrierte Schaltungen IIS  
Eichler, Uwe  orcid-logo
Fraunhofer-Institut für Integrierte Schaltungen IIS  
Project(s)
Prototyping- und Test-Zentrum für Systeme der Künstlichen Intelligenz am Fraunhofer-Institutsteil Entwicklung Adaptiver Systeme (EAS) Dresden  
Funder
Freistaat Sachsen  
Conference
edaWorkshop 2026  
File(s)
Download (2.7 MB)
Rights
Use according to copyright law
DOI
10.24406/publica-8700
Language
English
Fraunhofer-Institut für Integrierte Schaltungen IIS  
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