Demonstration of E/D-Mode Logic Circuits in a Four-Pole 20-nm InGaAs HEMT-on-Silicon Technology using Back-Gate Biasing

We present enhancement- and depletion-mode digital logic gates and circuits with back-gate biasing in a Four-pole high-electron-mobility transistor on Silicon technology. This work uses a 20-nm gate-length InGaAs HEMT-on-Si with the option to place an electron-beam-lithography defined back-gate below the InGaAs channel by wafer bonding. By applying back-gate bias, the threshold voltage is modulated to convert normally depletion-mode devices into enhancement-mode devices, without altering the physical structure or processing steps. The back-gated RF transistors are used directly to implement digital logic gates such as NOT, NAND, and NOR, as well as a D-LATCH circuit, and are demonstrated using the E/D logic approach. Additionally, the effect of back-gate biasing on the power consumption of logic gates is analyzed. The proposed circuits provide the opportunity to integrate logic components with state-of-the-art RF circuits monolithically.