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  4. A Current Mirror Based Read Circuit Design with Multi-Level Capability for Resistive Switching Devices
 
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2024
Conference Paper
Title

A Current Mirror Based Read Circuit Design with Multi-Level Capability for Resistive Switching Devices

Abstract
This paper presents a read circuit design for resistive memory cells based on current mirrors. The circuit utilizes high-precision current mirrors and reference cells to determine the state of resistive memory using comparators. It offers a high degree in adaptability in terms of both resistance range and number of levels. Special emphasis was put on device protection to prevent accidental programming of the memory during read operations. The realized circuit can resolve eight states with a resolution of up to 1 k Ω, realizing a digitization of the analog memory information. Furthermore, the integration in a complete memory macro is shown. The circuit was realized in a 130 nm-process but can easily be adapted to other processes and resistive memory technologies.
Author(s)
Pechmann, Stefan
Technische Universität München
Pérez, Eduardo
Institut fur innovative Mikroelektronik (IHP)
Wenger, Christian
Institut fur innovative Mikroelektronik (IHP)
Hagelauer, Amelie M.  
Fraunhofer-Einrichtung für Mikrosysteme und Festkörper-Technologien EMFT  
Mainwork
2024 International Conference on Electronics Information and Communication Iceic 2024
Conference
2024 International Conference on Electronics, Information, and Communication, ICEIC 2024
DOI
10.1109/ICEIC61013.2024.10457188
Language
English
Fraunhofer-Einrichtung für Mikrosysteme und Festkörper-Technologien EMFT  
Keyword(s)
  • analog design

  • current mirror

  • read circuit

  • resistive memory

  • RRAM

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