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Patent
Title

Processing crossbar semiconductor device

Abstract
There is disclosed a processing crossbar semiconductor device for processing an input vector a weight tensor, to derive an output vector as processed version of the weight tensor, the weight tensor having a plurality of weights, the crossbar processing device being configured to process each input electric value of an array of input electric values representing the input vector, the processing crossbar semiconductor device comprising: a set of weighting elements (101) arranged according to element columns and elements rows, each weighting element corresponding to a weight of the weight tensor, wherein the set of weighting elements is partitioned among a plurality of blocks (102), the plurality of blocks (102) being arranged according to super columns (108) and super rows (106) in such a way that each super row includes a plurality of immediately subsequent element rows and each super column includes a plurality of immediately subsequent element columns; a plurality of block output buses, each being associated with, and connected to, a plurality of blocks in the respective super row without being connected to blocks associated with, and connected to other super row, each block output bus including a plurality of block output lines, wherein each block of the plurality of blocks is configured, when activated, to weight input electric values of the array of input electric values by corresponding weights of the weight tensor, to provide electric weighted values to the block output bus associated with the super row of which the block is part; and a plurality of analog accumulation elements, each electrically connected with a block output line, to thereby provide a respective electric accumulated weighted value from the electric weighted values obtained from the corresponding element columns of a plurality of activated blocks in the super row associated with the block output line, to derive an array of accumulated weighted output values which form the output vector.
Inventor(s)
Kundu, Bijoy
Fraunhofer-Institut für Integrierte Schaltungen IIS  
Müller, Roland
Fraunhofer-Institut für Integrierte Schaltungen IIS  
Link to Espacenet
https://worldwide.espacenet.com/publicationDetails/biblio?DB=EPODOC&II=0&ND=3&adjacent=true&locale=de_EP&FT=D&date=20250306&CC=WO&NR=2025045366A1&KC=A1
Patent Number
WO2025045366 A1
Publication Date
March 6, 2025
Language
English
Fraunhofer-Institut für Integrierte Schaltungen IIS  
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