Entwurfsautomatisierung mit Layout-Generatoren für die frühzeitige Berücksichtigung von Parasitäten in A/MS-IC-Designs

Presentation of our EDA development activities and cooperation within the funded project HoLoDEC. The first part gives an overview of our Intelligent IP generator approach that enables a customized automation of design and migration of analog IC building blocks, and together with layout templates and code generation also a user-centric reuse and layout synthesis flow. In the second part we demonstrate how these generators allow an early analysis and optimization of parasitic layout effects.