Design of hardware accelerators for optimized and quantized neural networks to detect atrial fibrillation in patch ECG device with RISC-V

Atrial Fibrillation (AF) is one of the most common heart arrhythmias. It is known to cause up to 15 % of all strokes. In current times, modern detection systems for arrhytmias, such as single-use patch electrocardiogram (ECG) devices, have to be energy efficient, small, and affordable. In this work, specialized hardware accelerators are developed. First, an artificial neural network (NN) for the detection of AF is optimized. Special attention is given to the minimum requirements for the inference on a RISC-V-based microcontroller. Hence, a 32-bit floating-point-based NN was analyzed. To reduce the silicon area needed, the NN was quantized to 8-bit fixed-point datatype (Q7). Based on this datatype, specialized accelerators are developed. Those accelerators include single-instruction multiple-data (SIMD) hardware as well as accelerators for activation functions such as sigmoid and hyperbolic tangent. Additionally, e-function is implemented to accelerate the use of e.g. softmax activation function. To compensate the losses of quantization, the network is expanded and optimized for run-time and memory requirements. The resulting NN has a 7.5 % lower run-time in clock cycles (cc) without the accelerators and 2.2 percentage points (pp) lower accuracy compared to a floating-point-based net, while requiring 65 % less memory. With the specialized accelerators the inference run-time was lowered by 87.2 % while the F1-Score decreased by 6.1 pp. Implementing the Q7 accelerators instead of the floating-point unit (FPU), the silicon area needed for the microcontroller in 180 nm-technology is below 1 mm 2.