A flow for parasitics extraction in 3D-systems

Due to high integration density in 3D-Systems parasitic effects, which are originally not taken into account during design-phase, has a growing influence on the behavior of the entire system. Therefore, the influences of these effects have to be minimized within the design process. In the following a hierarchical modeling based flow for parasitic extraction of capacitance in 3D-Systems is described. The flow contains layout data import, translation and export data to our own hierarchical XML-based description, and electromagnetic calculations for capacitance extraction.