Fehleranalyse für DRAM Teilschaltungen durch Extraktion von Layout Parasitics

In this work essential parts of a DRAM circuit are studied with respect to their transient behavior in the presence of defects. A certain dynamic failure mechanism resulting in timing mismatches of signals is addressed. The necessary fault lists for the analog fault simulations take the circuit's layout geometry into consideration. The fault lists are generated with the aid of parasitic element extraction tools. The establishment of a mapping between the circuit layout and the electrical network reveals new facts about the robustness of design and the efficiency of existing test solutions.