Demonstrating an FPGA implementation of a full HD real-time HEVC decoder with memory optimizations for range extensions support

The novel High Efficiency Video Coding (HEVC) standard targets a broad set of different video formats ranging from QVGA up to Ultra-HD (4Kp60) resolutions. Especially the high spatial and temporal resolutions combined with the high algorithmic complexity makes implementing encoders and decoders a challenging task. Existing software based implementations on multi-core CPUs and/or DSPs suffer from real-Time constraints, power dissipation and hardware costs of these systems. In this paper a hardware implementation of a Full HD capable H.265/HEVC video decoder is presented targeting these constraints. The demonstrated video decoder incorporates recent standard improvements, namely H.265/HEVC version 2, by supporting enhanced video format range extensions for high quality video applications.