Aspects of chip/package interaction and 3-D integration assessed by the investigation of crack and damage phenomena in low-k BEoL stacks

Miniaturization and increasing functional integration push the development of feature sizes of advanced CMOS down to the nanometer range. New low-k and ultra low-k materials in Back-end of line (BEoL) structures cause new challenges for reliability analysis and prediction, in addition. A combined numerical/experimental approach will be explained towards optimizing fracture and fatigue resistance of BEoL-structures by making use of bulk and interface fracture concepts. The risk of near-chip-edge and near-bump cracking in BEoL-structures with lead-free as well as copper-pillar interconnects is analyzed and optimized under chip package interaction (CPI) and FC-reflow-soldering, in particular.