Reusable design of inter-chip communication interfaces for next generation of adaptive computing systems
Abstract
The SoC (System-on-Chip) technology is used in small and flexible consumer electronic devices. SoCs include one or more microcontroller, memory, programmable logic, and the input/output logic control. Additionally, sophisticated SoCs support partial dynamic reconfiguration. Those are preconditions to build the next generation of adaptive computing systems which make it possible to implement selforganizing systems that are self-configuring and self-optimizing. The design of applications and the development of tools for system design are a great challenge. In this paper we describe an approach that is used to support the design of applications by generator tools. This approach allows the re-use and the generation of communication interfaces between the components in partial run-time reconfiguration (pRTR) systems. The generator tool approach based on a methodology which enables a formal representation of adaptive systems and its timing schedule control. We prove our methodology and generator approach by applications from the field of signal processing.
