Highly ionized sputter deposition into through silicon vias with aspect ratios up to 15:1

Despite the many advantages of smaller form factors, higher bandwidth, lower latency, reduced power consumption and the potential for heterogeneous integration that have been touted for 3D-IC and 2.5D-IC designs, there are still relatively few products using these architectures in the marketplace. This is primarily due to the high cost associated with fabricating these structures. This paper describes physical vapor deposition (PVD) equipment and processes that were developed to deposit metal barriers and copper seed layers into high aspect ratio through silicon vias (TSVs) cost-effectively.