Contactless testing of digital integrated circuits using crystal potential contrast

This paper deals with a non-destructive and contactless test-method of a digital integrated CMOS circuit via the liquid crystal potential contrast (LCPC) technique. The LCPC has been developed from the well known field-induced DAP-effect leading to a test set-up which is economical and easy to be handled. The test set-up permits the observation of the logical states of internal circuit nodes by different test methods. Apart from usual test methods (DC-mode and AC-mode) a new method being called DEBUG-mode is presented. This mode allows the analysis of the functional behaviour on gate level and the indirect examination of the timing. The performance of a test process including these methods is discussed by means of a faulty part of a circuit. It is pointed out that by this test process the location of failure can be pinpointed on gate level and its origin explained.