Cost effective flip chip assembly and interconnection technologies for large area pixel sensor applications

Much of the cost of manufacturing pixel detectors is due to bumping and flip chip assembly of the readout chips onto sensor tiles, even if it is done on wafer level. To address this issue, Fraunhofer IZM investigated two new technological approaches, namely screen printing using dry film resist and chip-to-wafer assembly. In the first approach, solder bumps with diameters of 80 and 25 m in pitches of 110 and 60 m, respectively, were produced by screen-printing solder paste using a photo-structured dry film resist. Results indicated that the technology is a viable high yield and low cost bumping process. The second approach was developed to decrease the number of manual handling steps in pixel module manufacturing, which is critical for reducing processing time and cost. Here, chip designs on 200 mm readout chip (ROC) wafers and 150 mm sensor wafers were especially adapted for chip-to-wafer assembly and to ensure that the interconnection yield and reliability could be te sted. After bumping and dicing of the readout chip wafer and UBM plating on the sensor wafer, individual dice were flip chip mounted on the pre-diced sensor wafer. This paper describes the technological steps, key processing parameters and first results for both technologies.