FPGA based high-speed system solutions for innovative maskless lithography systems

Maskless lithography is one of the possible solutions to manage the escalating mask costs and demands for faster production cycles. One of the major issues with the maskless lithography technology however is the management and transfer of the enormous data volumes required to define the chip structures. Ensuring competitive and reliable operation requires dedicated preparation and buffering of the lithography data to be transmitted to the exposure unit. An optimized dedicated architecture and careful signal integrity design for proper functionality are needed due to the high data rates and the highly parallelized system operation. This paper presents the implementation aspects and the design of a high-speed transmission system solution for maskless lithography systems. The introduced solution treats a field programmable gate array (FPGA) based implementation for a latency-sensitive high speed lithography system.