Design and analysis of a W-band multiplier chipset

The design and analysis of a multiplier chipset with an output at W-band is presented. The MMIC designs have been fabricated on a 0.13 m AlGaAs/InGaAs/GaAs pHEMT process. Particular emphasis has been placed on EM analysis of key components and the optimization of models suitable for use in circuit simulators based on the EM simulations. The results show a first iteration design with an on-wafer saturated output power of 20.2 dBm at 92 GHz and greater than 18 dBm over a 9% bandwidth from 87.5 - 95.5 GHz.