Inference runtime of a neural network to detect atrial fibrillation on customized RISC-V-based hardware

As a common heart arrhythmia, atrial fibrillation(AF) is considered to be responsible for up to 15 % of allstrokes. For the diagnosis of AF, long term electrocardiogram(ECG) recordings are widely used. These recordings are ob-tained by Holter monitors or state-of-the-art patch ECG de-vices. Energy efficiency is of critical importance to enablethe use of the patch ECG devices for several days withoutchanging batteries or patches, while maintaining a small andlightweight design. Energy consumption of microcontrollersstrongly depends on their operating frequency. Hence theybenefit from a minimal software run time in clock cycles. Inthis work the impact of customized hardware in combinationwith structural optimization on inference runtime of a neu-ral network (NN), for the detection of AF and embedded ina patch ECG device, is investigated. The combination of opti-mized NN structure with the optimized hardware requires only13 % of the runtime compared to the original NN, while theaccuracy is increased by 0.5 percent points.