ASICs for prototyping of pulse-density modulated neural networks

Two alternative ways are presented for creating dedicated neural hardware realization based on pulse-density modulation. The first approach emphasizes fast prototyping of neural systems in a conventional digital microprocessor environment. It uses an ASIC cell library in combination with a sea-of-gates template to produce testable integrated neural circuits with off-chip learning. Typical single-chip network sizes range from 18 (eighteen) neurons with 846 (eighthundred and fourty-six) synapses to 110 (onehundred ten) neurons with 550 (fivehundred and fifty) synapses. Larger network sizes can be obtained by concatenation.