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  4. HZO-based Nonvolatile SRAM Array with 100% Bit Recall Yield and Sufficient Retention Time at 85°C
 
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2024
Conference Paper
Title

HZO-based Nonvolatile SRAM Array with 100% Bit Recall Yield and Sufficient Retention Time at 85°C

Abstract
For the first time, a 16-Kbit nonvolatile SRAM (NVSRAM) array based on a metal/ferroelectric/metal capacitor using a sub-10-nm-thick HfZrOx (HZO) layer has been experimentally demonstrated to obtain 100% bit yield. This capacitor is formed using the same integration process as that of a previously developed ferroelectric random-access memory (FeRAM) array on the same wafer. Its sequential operations of nonvolatile data store (Store), cutoff of power supply (power-gating: PG), and data recall (Recall) are completely executed employing a robust Recall sequence, achieving 100%-bit recall after a 200-s PG period at 85 ° C even with sufficiently low operation voltage. The results indicate that our HZO-based NVSRAM and FeRAM hybrid memory system can provide ultra-low power advantages in a System-on-Chip for Internet of Things edge computing.
Author(s)
Shuto, Yusuke
Okuno, Jun
Yonai, Tsubasa
Ono, Ryo
Reinig, Peter  
Fraunhofer-Institut für Photonische Mikrosysteme IPMS  
Lederer, Maximilian
Fraunhofer-Institut für Photonische Mikrosysteme IPMS  
Seidel, Konrad  
Fraunhofer-Institut für Photonische Mikrosysteme IPMS  
Alcala, Ruben
Mikolajick, Thomas
Schroeder, Uwe Paul
Umebayashi, Taku
Akiyama, Kentaro
Mainwork
IEEE Symposium on VLSI Technology and Circuits 2024  
Conference
Symposium on VLSI Technology and Circuits 2024  
DOI
10.1109/VLSITechnologyandCir46783.2024.10631328
Language
English
Fraunhofer-Institut für Photonische Mikrosysteme IPMS  
Keyword(s)
  • ferroelectric capacitor

  • hafnium oxide

  • nonvolatile SRAM

  • power-gating

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