Design of low-resistance and area-efficient GaN-HEMTs for low-voltage power applications

This work analyzes different layouts for low-resistance and area-efficient GaN-HEMT devices for low voltage power applications. The current distribution in interdigital comb and matrix structures is investigated and geometry parameters are optimized to achieve the lowest possible area-specific on-state resistance for given technology limits. A new model is analytically derived to investigate the static on-state behavior in matrix structures. Fabricated large area power transistors feature low specific on-state resistances RON∙A of 0.61 mO∙cm² for the comb structure, a reduced specific on-state resistance of 0.37 mO∙cm² for the matrix structure, and a further reduced specific on-state resistance of0.23 mO∙cm² for a high-density, fully symmetrical matrix structure.