Implementation of an FPGA-based Time-to-Digital Converter

Quantum Key Distribution (QKD) systems require time-tagging by Time-to-Digital Converter (TDC) with high accuracy in the range of tens of picoseconds. FPGA delivers a flexible platform for exploring various QKD protocols with lower costs and relatively good performance. In this research, an FPGA-based TDC for a QKD system is implemented and evaluated based on the investigations of open-source projects. On our Xilinx ZYNQ-7000 FPGA, the CARRY4-based delay line architecture
provides a fine-time interpolation with a resolution of 11.1 ps, a nonlinear property of [-8.2, 16.1] ps DNL and [-30.0, 42.0] ps INL, a measurement throughput rate of 62.1 MS/s. The application specific metrics are generally met with acceptable deviations for the QKD application.