Compact electro-thermal simulation of ESD-protection elements

Numerical simulations at the circuit level can improve the understanding of the behaviour of protection structures under system aspects. Full protection circuits with the influence of HBM ESD tester parasitics and additional parasitic elements in the circuitry have been investigated. Compact electro-thermal models for single protection elements (diodes and snapback nMOSFETs) have been developed. They help to explain differences between expected ESD-hardness and HBM-failure thresholds of protection structures.