A novel simulation approach for partial runtime reconfigurable hardware

In this paper we propose a method for the simulation of hardware which is partially reconfigurable at run time. Based on a strategy for the appropriate partitioning of simulation tasks, our method utilizes a usual gate-level simulator and exploits an approach for the coupling of particular simulation results. Exemplarily, we demonstrate the underlying principles of our method for a simple reconfigurable design. In addition, we present experimental results achieved for a more extensive datapath performing the syndrome computation of a Reed Solomon Decoder.