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  4. MESH: Explicit and flexible generation of analog arrays
 
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2017
Conference Paper
Title

MESH: Explicit and flexible generation of analog arrays

Abstract
Analog layout design is a costly and error-prone task since analog synthesis is still far from applicable. It is expected that procedural bottom-up generators managing constructive tasks will be part of future synthesis flows. Generators contain expert knowledge implicitly within complex and hard-to-understand source code. Due to a lack of explicit layout definition and uncaptured design intent, generator layouts can hardly be adapted by constructive algorithms directly. Thus, synthesis flows need to adapt layout blocks by varying generator parameters which results in computation-expensive optimization. This paper introduces MESH-a software structure to define detailed and flexible layout generators explicitly. Using MESH, just a few lines of code describe complex layouts while all relations and design intents, such as element positions and routing styles, are captured through abstract commands. As a result, generators are created fast with less programming errors, and constructive algorithms can modify the generator structure directly.
Author(s)
Prautsch, Benjamin  orcid-logo
Fraunhofer-Institut für Integrierte Schaltungen IIS  
Eichler, Uwe  orcid-logo
Fraunhofer-Institut für Integrierte Schaltungen IIS  
Reich, Torsten  
Fraunhofer-Institut für Integrierte Schaltungen IIS  
Lienig, Jens
TU Dresden
Mainwork
PRIME 2017, 13th Conference on Ph.D. Research in Microelectronics and Electronics. Conference proceedings  
Project(s)
Things2Do
PRIME
Funder
Bundesministerium für Bildung und Forschung BMBF (Deutschland)  
Bundesministerium für Bildung und Forschung BMBF (Deutschland)  
Conference
Conference on Ph.D. Research in Microelectronics and Electronics (PRIME) 2017  
International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) 2017  
Open Access
File(s)
Download (1.66 MB)
Rights
Use according to copyright law
DOI
10.1109/SMACD.2017.7981572
10.24406/publica-r-397278
Additional link
Full text
Language
English
Fraunhofer-Institut für Integrierte Schaltungen IIS  
Keyword(s)
  • IntelligentIP

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