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  4. 3D Wafer Level Integration - Status and Requirements
 
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2015
Book Article
Title

3D Wafer Level Integration - Status and Requirements

Abstract
According to the increasing application driven demands on functionality, per-formance, miniaturization and reliability for microelectronic systems, System in Packages (SiP) using 3D integration are key elements for advanced micro-electronic packaging. Key elements for 3D wafer level SiPs are the formation of Through Silicon Vias (TSVs) and their process integration into active devices as well as silicon interposer as a key enabler for 3D Systems.
Author(s)
Wolf, M. Jürgen
Mainwork
Microelectronic Packaging in the 21st Century  
Language
English
Fraunhofer-Institut für Zuverlässigkeit und Mikrointegration IZM  
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