3D Wafer Level Integration - Status and Requirements
Abstract
According to the increasing application driven demands on functionality, per-formance, miniaturization and reliability for microelectronic systems, System in Packages (SiP) using 3D integration are key elements for advanced micro-electronic packaging. Key elements for 3D wafer level SiPs are the formation of Through Silicon Vias (TSVs) and their process integration into active devices as well as silicon interposer as a key enabler for 3D Systems.
