Lifetime modelling of sintered silver interconnected power devices by FEM and experiment

In this paper, the research is focused on lifetime analysis and prediction of silver sintered power devices by experiment and numerical simulation. As researches are emerging on the field of lead-free interconnect technology, silver sintering become an alternative interconnect technology to standard solders. This technology differs from other interconnect technologies because of it's improved thermal and mechanical properties. Aluminum cladded copper core (CucorAl) wires have been used to prevent early fail of top contacts. Material degradation due to thermal fatigue in the sintered silver still influences the reliability in the interconnect, in particular for high temperature swings upcoming with wide bandgap semiconductors. Plastic deformation is observed in sintered silver interconnect which depends on time and temperature. This research work presents combined experimental and finite element analysis (FEA) results for developing a lifetime model for the sintered silver power modules. Different parameters such as porosities on the sintered silver layer, substrates, plastic and creep constitutive laws, die thickness and sizes, should be considered during the development of lifetime model. In this investigation, Insulated-gate bipolar transistor (IGBT) chips are integrated on different substrates such as printed circuit board (PCB- Help H), insulated metal substrate (IMS), copper lead frame (Cu-lead frame) and direct copper bond (DCB) by silver sintered interconnect. Failure modes such as wire bond lift-off and die bond degradation are observed during this research.