Theoretical and practical minimum of the power consumption of 3 ADCs in SC technique

In this paper the theoretical and practical minimum of the power consumption is investigated for 3 ADC architectures, which are predestined for low conversion speed and applications in low-power sensor readout circuits. The analysis is made for the switched capacitor versions of the SAR ADC, cyclic ADC and sigma-delta modulator. The theoretical limit of the power efficiency is investigated by a commonly used figure of merit (FOM). As a case study two low-power ADCs fabricated in different technologies a technology-independent FOM is introduced.