2010
Poster
Title

Trench gate integration into planar technology for reduced on-resistance in LDMOS devices

Title Supplement
Poster presented at Symposium on Power Semiconductor Devices & ICs 2010, Hiroshima, Japan
Author(s)
Erlbacher, T.  
Rattmann, G.  
Bauer, A.J.
Frey, L.
Conference
File(s)
Rights
Use according to copyright law
DOI
Language
English
Keyword(s)