Impact of post-trench processing on the electrical characteristics of 4H-SiC trench-MOS structures with thick top and bottom oxides

This study focuses on the evaluation of different post-trench processes (PTPs) for Trench-MOSFETs. Thereto, two different types of inert gas anneals at process temperatures above 1250 degC are compared to a sacrificial oxidation as PTP. The fabricated 4H-SiC Trench-MOS structures feature a thick silicon dioxide (SiO 2) both at the wafer surface (`top') and in the bottom of the trenches (`bottom') in order to characterize only the thin gate oxide at the trenched sidewalls. It is shown that an inert gas anneal at a process temperature between 1400 degC and 1550 degC yields uniform current/electric field strength (IE) values and excellent dielectric breakdown field strengths up to 12 MV/cm using a SiO 2 gate oxide of approximately 40 nm thickness. Charge-to-breakdown (QBD) measurements at a temperature T of 200 degC confirm the necessity of a high temperature inert gas anneal after 4H-SiC trench etching in order to fabricate reliable Trench-MOS devices. QBD values up to 16.2 C/cm 2 have been measured at trenched and high temperature annealed sidewalls, which is about twice the measured maximum QBD value of the corresponding planar reference MOS structure. The capacitive MOS interface characterization points out the need for a sacrificial oxidation subsequent to a high temperature inert gas anneal in order to ensure a high quality MOS interface with excellent electrical properties.