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2014
Conference Paper
Title
Design and evaluation of realizable and compact low-impedance transmission lines for two top-metal-layer semiconductor processes
Abstract
This paper compares three different narrow 12.5Ω lines regarding their insertion loss. All three lines are realizable on a two top-metal-layer semiconductor process. It turns out that an artificial LC/ telegrapher line, composed of high and low impedance line elements, has the lowest loss of all three presented lines. The investigation, which is based on EM simulations is verified by S-Parameter measurements of all three lines up to 325 GHz. For a length of 315 µm the LC line shows an insertion loss of 2.5 dB@200 GHz.
Author(s)