Threshold voltage engineering by lanthanide doping of the MOS gate stack

With the replacement of traditional polysilicon and silicon dioxide by metal gates and high-k dielectrics, respectively, in the MIS gate stack for the 45 nm technology node, higher than expected device threshold voltages have been observed due to the effect of Fermi-level pinning. While the debate as to the exact cause of Fermi-level pinning is ongoing, several attempts (capping layers, new gate metal compositions) have been made to curb this effect. In this paper, the tuning of metal gate work function by ion implantation is investigated as a tool for controlling the threshold voltage. Lanthanide incorporation is used to achieve a flat-band voltage shift of more than -1 V for n-MOS capacitors. It is shown that by adjusting dose and energy, the flat-band voltage shift can be tuned to a desired value, without substantial damage to the insulating quality of the gate. This translates to an effective shift in the threshold voltage.