Architecture and circuit technology of a two-dimensional DCT for video signal coding

Suitable parallel architectural concepts for reducing data volume for video signals in orthogonal functional space (transform coding) are presented. This is followed by their translations into circuit structures as regular as possible for VLSI implementation. The proposed structure is characterized by optimal regularity with short connections between the individual processor units and enables calculations of the Discrete Cosine Transform coefficients in real time for use in HDTV systems with pixel frequencies up to 70 MHz. The device can be implemented in 1.5 mu m CMOS technology.