• English
  • Deutsch
  • Log In
    Password Login
    Research Outputs
    Fundings & Projects
    Researchers
    Institutes
    Statistics
Repository logo
Fraunhofer-Gesellschaft
  1. Home
  2. Fraunhofer-Gesellschaft
  3. Scopus
  4. Technology for Sequential Integration of HPA and LNA on Stacked GaN Layers for 3D Packaging of Next Gen Miniaturized Power RF Transceiver Front Ends
 
  • Details
  • Full
Options
2026
Conference Paper
Title

Technology for Sequential Integration of HPA and LNA on Stacked GaN Layers for 3D Packaging of Next Gen Miniaturized Power RF Transceiver Front Ends

Abstract
In this work we propose a disruptive technological approach based on 3D sequential integration of high-power amplifiers (HPAs) and low-noise amplifiers (LNAs) together with RF MEMS switches. Overall scope is to enable drastic improvements in reduction of size weight and power consumption (SWaP) for next generation power RF front ends operating up to Ka band for airborne future multi-mission radars. Core of the integration concept is the stacking of a second gallium nitride (GaN) layer for the fabrication of LNA and RF MEMS switch on top of a first GaN layer with already present HPA components. The preparation of the second GaN layer is done by extreme thinning of wafers with a GaN epitaxy layer on temporary carrier wafers, followed by the permanent adhesive bonding of the thin GaN layer to the wafer with the already processed HPA components and the final release of the temporary carrier wafer from the transferred GaN layer. Bonding of silicon interposer with TSVs enables final encapsulation of the GaN stacked components and vertical signal feeding. The entire integration approach is successfully shown on 100 mm wafers with test circuits that allow subsequent electrical characterization of the signal path from the first GaN layer, through the second GaN layer as well as through the silicon interposer. The paper will discuss in detail the related technological process flow for building the 3D sequential integration stack as well as generated results such images after certain process steps, first electrical test data, considerations of thermal performance and also process improvement options.
Author(s)
Zoschke, Kai  
Fraunhofer-Institut für Zuverlässigkeit und Mikrointegration IZM  
Oppermann, Hermann  
Fraunhofer-Institut für Zuverlässigkeit und Mikrointegration IZM  
Stavrinidis, Antonis
Foundation for Research and Technology-Hellas (FORTH)
Makris, Nikolaos
Foundation for Research and Technology-Hellas (FORTH)
Komninou, Philomela
Aristotle University of Thessaloniki
Florini, Nikoletta
Aristotle University of Thessaloniki
Fioravanti, Paolo
Circuits Integrated Hellas SA Kifisia
Lourandakis, Errikos
Circuits Integrated Hellas SA Kifisia
Heusdens, Bruno
Taipro Engineering Lambermont
Hertay, Adrien
Taipro Engineering Lambermont
Abo Ras, Mohamad
Berliner Nanotest und Design GmbH
Ziaei, Afshin
Thales Research and Technology
Mainwork
IEEE 76th Electronic Components and Technology Conference, ECTC 2026. Proceedings  
Conference
Electronic Components and Technology Conference 2026  
DOI
10.1109/ECTC51846.2026.00377
Language
English
Fraunhofer-Institut für Zuverlässigkeit und Mikrointegration IZM  
Keyword(s)
  • 3D Integration

  • Packaging of Power RF Transceiver

  • TSV Silicon Interposer

  • Wafer Bonding

  • Wafer Level Packaging

  • Cookie settings
  • Imprint
  • Privacy policy
  • Api
  • Contact
© 2024