Multi-level hierarchical analogue fault simulation

In this paper the extensions of our analogue fault simulator `aFSIM' to a multi-level hierarchical analogue fault simulation tool are described. Due to these extensions it is now possible to fault-simulate larger analogue circuits. In addition mixed-signal circuits including a not too large amount of digital circuitry can also be fault-simulated. The term `multi-level hierarchical analogue fault simulation' comprises the usage of behavioural models for components together with components described at the transistor-level, fault injection at different abstraction levels, and a hierarchical handling of both different descriptions of the circuit components and faults during the fault simulation process. Multi-level hierarchical analogue fault simulation is an important means to tackle the complexity of analogue circuits for providing test signals with a high fault and defect coverage.