Integrated Multi-Stage Cascode Structure for Lateral High-Voltage GaN Power Transistors

This work demonstrates an integrated multi-stage cascode structure for lateral high-voltage transistors in a GaN-on-SiC power technology. The functional principal, the intrinsic device structure and the extrinsic chip layout is presented and is investigated. The fabricated device demonstrator features a breakdown measurement up to 1000 V, an maximum on-state current of ID,MAX = 10 A, and on-state resistance of about RON = 1 Omega.