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November 22, 2022
Video
Title
Automatic Generation of 22FDX OpAmp Designs in the Virtuoso® Suite by Incorporating ID-Xplore™ of Intento Design with IIP of Fraunhofer IIS/EAS
Abstract
With increased device scaling below 45nm, the impact of layout dependent parasitics, in addition to interconnect ones, becomes increasingly difficult to handle. In order to gain early awareness of these effects on design performance, we present an automated flow based on Cadence® Virtuoso® for fast design space exploration, generation of multiple floorplans of sized operational amplifiers, and automatic generation of their final layout views. The generated layouts are automatically routed using a straight-forward routing scheme for faster runtime. The sized designs and their routed layouts are fully generated in two minutes each. Our presented flow combines the following tasks: detailed design space exploration using ID-Xplore™ from Intento Design, an IPC interface to send SKILL commands to Cadence®, template-based layout generators based on the IIP tool from Fraunhofer IIS/EAS, oaScript: the Python scripting language of OpenAccess, and the open source rectangle-packer. In this fully automated flow, the execution of all aforementioned steps is started by a single SKILL command.
As a case study, several sized designs and layout variants of an operational amplifier have been generated in GF-22FDX in a matter of minutes. We conclude that designers are provided the possibility to enhance early decision-making using the proposed method. Combined with the Virtuoso® flow, designers will achieve successful chip realization faster and reduce respin count.
As a case study, several sized designs and layout variants of an operational amplifier have been generated in GF-22FDX in a matter of minutes. We conclude that designers are provided the possibility to enhance early decision-making using the proposed method. Combined with the Virtuoso® flow, designers will achieve successful chip realization faster and reduce respin count.
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