Post-CMOS 3D-integration of a nanopellistor

To further optimize micro pellistors and reduce the required chip area, one possibility is to fabricate the sensor on top of the integrated circuit (IC). Therefore, a sacrificial layer process developed by the Fraunhofer IMS combining deep reactive ion etching (DRIE) and atomic layer deposition (ALD) is modified. First fundamentals of pellistors and Joule heating are described. Then simulations to determine ideal heater shapes are presented and an approach for a process to fabricate pellistors on top of an IC is introduced.