A tailored design partitioning method for hardware emulation

Partitial run time reconfiguration (pRTR) enables a dynamic replacement of design modules to optimize the resource utilization of FPGA-based hardware emulation. This requires an appropriate partitioning of the entire design into particular hardware modules. There exist various methods to partition a design at functional as well as at structural level. In this paper, an adapted functional method to partition the design into independent modules is proposed. In consideration of typical functional modules (e.g. controller, DSP parts, memory) of a System-on-chip (SoC), the design is partitioned. The method is especially suited if the design consists of regular structures (multiprocessor design, vector-DSP). The results of the design partitioning are using to determine significant parameters of a generic emulator environment implemented on a state-of-the-art FPGA platform. The benefits are a decreasing number of run time reconfigurations and an improved utilization of the FPGA resources.